IP Library Granted Patent US 9,006,745
Granted Patent B2
US 9,006,745 · App. 13/522,216 · Granted Apr 14, 2015

Semiconductor device and fabrication method thereof

Inventors: Takeyoshi Masuda (Osaka, JP); Keiji Wada (Osaka, JP); Toru Hiyoshi (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/66068H01L29/1095H01L29/7802H01L29/7813H01L21/0465H01L29/0623H01L29/1608H01L29/45
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Quick Facts
Patent No.
US 9,006,745
App. No.
13/522,216
Granted
Apr 14, 2015
Kind
B2
Abstract

An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Claims (11)

1. A method of fabricating a semiconductor device comprising the steps of:

preparing a substrate made of silicon carbide,

forming an epitaxial growth layer made of silicon carbide on said substrate,

forming a body region at said epitaxial growth layer,

forming a gate insulation film made of an insulator to come into contact above said epitaxial growth layer, and

forming a gate electrode to which voltage is applied to form an inversion layer in a region of said body region in contact with said gate insulation film,

said step of forming a body region including the steps of

forming a mask layer having an opening on said epitaxial growth layer,

forming a first concentration region having a first impurity concentration at the region where said inversion layer is formed by applying ion implantation with said mask layer as a mask,

enlarging said opening by etching said mask layer, and

forming a second concentration region having a second impurity concentration differing from said first impurity concentration, adjacent to said first concentration region in a carrier mobile direction in said inversion layer, and at a region where said inversion layer is formed, by executing ion implantation using said mask layer having said opening enlarged as a mask.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2012
From: MASUDA, TAKEYOSHI; WADA, KEIJI; HIYOSHI, TORU
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 028547/0118 →
Priority Claims (1)
JP 2010-245187 · Nov 1, 2010 · national
Continuity (1)
Related Publication 20120280255A1 · Nov 8, 2012