IC class T0-T2 taps with and without topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.
1. An integrated circuit comprising:
(A) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead;
(B) a first test access port having a clock input connected to the first test clock lead and being free of the second test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the first test access port having class T0-T2 capabilities and being free of any topology selection logic; and
(C) a second test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port having class T0-T2 capabilities and including topology selection logic.
2. The integrated circuit of claim 1 in which the first test access port is connected in series with additional test access ports.
3. The integrated circuit of claim 1 in which the second test access port is connected in any one of Series, Star-4, and Star-2 Scan topologies.