Silicon wafer and fabrication method thereof
A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 μm to approximately 80 μm from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
1. A silicon wafer, comprising:
a first denuded zone formed with a depth ranging from approximately 20 μm to approximately 80 μm from a top surface of the silicon wafer; and
a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen within a range from approximately 10.5 to approximately 13 ppma (parts per million atom) uniformly distributed within a variation of 10% over the bulk area, and a density of bulk micro defect in the bulk area being greater than or equal to 5.43×10 6 ea/cm 2 and less than or equal to 1×10 7 ea/cm 2 ,
wherein the first denuded zone is a defect free zone;
the first denuded zone and the bulk area are obtained by performing a first rapid thermal process and a second rapid thermal process after the first rapid thermal process, a size of oxygen precipitate in the bulk area increasing during the second rapid thermal process, and by performing a first annealing process at a first temperature, and a second annealing process at a second temperature subsequent to the first annealing process, the second temperature being higher than the first temperature; and
the first rapid thermal process and the second rapid thermal process are performed at a temperature in a range of approximately 950° C. to 1150° C.
2. The silicon wafer of claim 1 , further comprising:
an epitaxial layer formed over the top surface of the silicon wafer through an epitaxial growth.
3. The silicon wafer of claim 1 , further comprising:
a second denuded zone formed below the bulk area with a predetermined depth from the backside in a direction of the top surface.
4. The silicon wafer of claim 3 , wherein the second denuded zone is formed with a depth ranging from approximately 20 μm to approximately 80 μm from the backside.
5. The silicon wafer of claim 1 , wherein the first denuded zone and the bulk area are obtained through a first annealing process performed for approximately 100 minutes to 200 minutes at a first temperature, and a second annealing process performed for approximately 100 minutes to 200 minutes at a second temperature subsequent to the first annealing process, the second temperature being higher than the first temperature.
6. The silicon wafer of claim 5 , wherein the first temperature corresponds to a temperature in a range of approximately 750° C. to 800° C., and the second temperature corresponds to a temperature in a range of approximately 1050° C. to 1150° C.
7. The silicon wafer of claim 1 , wherein the first rapid thermal process is performed at a first rapid thermal process temperature; the second rapid thermal process is performed at a second rapid thermal process temperature; and the second rapid thermal process temperature is lower than the first rapid thermal process temperature.
8. A silicon wafer, comprising:
a first denuded zone formed with a depth ranging from approximately 20 μm to approximately 80 μm from a top surface of the silicon wafer; and
a bulk area formed between the first denuded zone and backside of the silicon wafer, the bulk area having a concentration of oxygen within a range from approximately 10.5 to approximately 13 ppma (parts per million atom) uniformly distributed within a variation of 10% over the bulk area, and a density of bulk micro defect in the bulk area being greater than or equal to 5.43×10 6 ea/cm 2 and less than or equal to 1×10 7 ea/cm 2 ,
wherein the first denuded zone is a defect free zone; and
the first denuded zone and the bulk area are obtained by performing a first rapid thermal process for approximately 10 to 30 seconds and a second rapid thermal process for approximately 10 to 30 seconds after the first rapid thermal process, a size of oxygen precipitate in the bulk area increasing during second rapid thermal process, and by performing a first annealing process for approximately 100 minutes to 200 minutes at a first temperature, and a second annealing process for approximately 100 minutes to 200 minutes at a second temperature subsequent to the first annealing process, the second temperature being higher than the first temperature.
9. The silicon wafer of claim 8 , wherein the first rapid thermal process and the second rapid thermal process are performed at a temperature in a range of approximately 950° C. to 1150° C.
10. The silicon wafer of claim 8 , wherein the first temperature corresponds to a temperature in a range of approximately 750° C. to 800° C., and the second temperature corresponds to a temperature in a range of approximately 1050° C. to 1150° C.
11. The silicon wafer of claim 8 , further comprising:
an epitaxial layer formed over the top surface of the silicon wafer through an epitaxial growth.
12. The silicon wafer of claim 8 , further comprising:
a second denuded zone formed below the bulk area with a predetermined depth from the backside in a direction of the top surface.
13. The silicon wafer of claim 8 , wherein the second denuded zone is formed with a depth ranging from approximately 20 μm to approximately 80 μm from the backside.