IP Library › Granted Patent US 9,024,848
Granted Patent B2
US 9,024,848 · App. 14/465,295 · Granted May 5, 2015

Display device

Inventors: Junichi Yamashita (Tokyo, JP); Katsuhide Uchino (Kanagawa, JP)
Assignee: Sony Corporation
G09G3/3225G09G3/3233G09G3/3266G09G2300/0426G09G2300/0439G09G2300/0465G09G2300/0819G09G2300/0842G09G2300/0866G09G2310/0256G09G2320/043G09G2320/045G09G3/30G09G2300/08G09G2310/027G09G2310/06
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Quick Facts
Patent No.
US 9,024,848
App. No.
14/465,295
Granted
May 5, 2015
Kind
B2
Abstract

Any one of a write scanning line, a power source supply line, and a video signal line is structured as a subsidiary wiring disposed in the same layer as that having a lower electrode disposed therein. The subsidiary wiring is used in the power source supply line through which a power source drive pulse to be pulse-driven is transmitted, or other wirings (such as the write scanning line and the video signal line).

Claims (64)

1. A display device comprising:

a pixel array portion having a plurality of scanning lines, a plurality of signal lines, and a plurality of pixels disposed in a matrix, each of the plurality of pixels including a drive transistor for controlling a drive current, a sampling transistor, an electro-optic element, and a storage capacitor for holding information corresponding to a signal potential supplied from one of the plurality of signal lines via the sampling transistor,

wherein

each electro-optic element of the plurality of pixels has a lower electrode, an organic layer and an upper electrode laminated on the lower electrode in order,

a plurality of first wirings are disposed in the same layer as that having the lower electrodes wired therein, each of the plurality of first wirings being configured to supply an initialization voltage to the capacitor of a corresponding one of the plurality of pixels,

the plurality of scanning lines and the plurality of signal lines are wired in a first layer and a second layer, respectively, which are both different from the layer having the lower electrode wired therein,

for each of the plurality of pixels, at least one of the pixel elements thereof is arranged in an area that is at least partially covered in a layer-stacking direction by one of the plurality of first wirings,

the first wiring and the lower electrode are in the same plane as one another,

a second wiring is disposed in one of the first and second layers,

the second wiring is connected to the first wiring as a subsidiary wiring thereof, and

the signal lines extend in a first direction, the scanning lines extend in a second direction orthogonal to the first direction, and the first wiring line extends in the second direction.

2. The display device of claim 1 , wherein the first wiring extends in parallel to and covers in a layer-stacking direction one of the signal line and the scanning line.

3. The display device of claim 1 , further comprising a third wiring disposed in the third layer, wherein the third wiring is connected to the upper electrode as a subsidiary wiring thereof.

4. The display device of claim 1 , wherein the first wring is a power supply line configured to carry a first potential for supplying the initialization voltage to the capacitor and a second potential higher than the first potential for driving the electro-optic element.

5. A display device, comprising:

a pixel array portion having

a scanning line,

a signal line,

a first wiring, and

a pixel that includes a transistor and an electro-optic element,

wherein the signal line is wired in a first layer and the scanning line is wired in a second layer,

the first wiring is disposed in a third layer different from the first and second layers,

the electro-optic element has a lower electrode disposed in the third layer, an organic layer disposed on the lower electrode and an upper electrode disposed on the organic layer,

the first wiring is configured to supply an initialization voltage to the lower electrode of the electro-optic element via the transistor,

the first wiring and the lower electrode are in the same plane as one another,

a second wiring is disposed in one of the first and second layers,

the second wiring is connected to the first wiring as a subsidiary wiring thereof, and

the signal lines extend in a first direction, the scanning lines extend in a second direction orthogonal to the first direction, and the first wiring line extends in the second direction.

6. The display device of claim 5 , wherein the first wiring extends in parallel to and covers in a layer-stacking direction one of the signal line and the scanning line.

7. The display device of claim 5 , further comprising a third wiring disposed in the third layer, wherein the third wiring is connected to the upper electrode.

8. The display device of claim 5 , wherein the first wring is a power supply line configured to carry a first potential for supplying the initialization voltage to the capacitor and a second potential higher than the first potential for driving the electro-optic element.

9. A display device, comprising:

a pixel array portion having

a scanning line,

a signal line,

a first wiring, and

a pixel that includes a transistor and an electro-optic element,

wherein the signal line is wired in a first layer and the scanning line is wired in a second layer,

the first wiring is disposed in a third layer different from the first and second layers,

the electro-optic element has a lower electrode disposed in the third layer, an organic layer disposed on the lower electrode, and an upper electrode disposed on the organic layer,

the first wiring is configured to supply an initialization voltage to the lower electrode of the electro-optic element via the transistor,

the first wiring is arranged between a lower electrode of a first pixel row and a lower electrode of a second pixel row,

a second wiring is disposed in one of the first and second layers,

the second wiring is connected to the first wiring as a subsidiary wiring thereof, and

the signal line extend in a first direction, the scanning line extend in a second direction orthogonal to the first direction, and the first wiring line extends in the second direction.

10. The display device of claim 9 , wherein the first wiring extends in parallel to and covers in a layer-stacking direction one of the signal line and the scanning line.

11. The display device of claim 9 , further comprising a third wiring disposed in the third layer, wherein the third wiring is connected to the upper electrode.

12. The display device of claim 9 , wherein the first wring is a power supply line configured to carry a first potential for supplying the initialization voltage to the capacitor and a second potential higher than the first potential for driving the electro-optic element.

13. A display device comprising:

a plurality of signal lines formed in a first layer;

a plurality of scanning lines formed in a second layer;

a first wiring formed in a third layer;

a second wiring formed in the first layer; and

a plurality of pixels, each of the pixels includes a transistor and an electro-optic element,

wherein

the electro-optic element has a lower electrode disposed in the third layer, an organic layer disposed on the lower electrode, and an upper electrode disposed on the organic layer,

the second wiring is connected to the first wiring as a subsidiary wiring thereof through a contact formed in an interlayer film, is covered in a layer stacking direction by the first wiring, and extends in parallel to the first wiring, and

the first wiring is configured to supply an initialization voltage to the lower electrode of the electro-optic element via the transistor, and

the plurality of signal lines extend in a first direction, the plurality of scanning lines extend in a second direction orthogonal to the first direction, and the first wiring extends in the second direction.

14. The display device of claim 13 , wherein the first wiring extends in parallel to and covers in a layer-stacking direction one of the signal line and the scanning line.

15. The display device of claim 13 , further comprising a third wiring disposed in the third layer, wherein the third wiring is connected to the upper electrode.

16. The display device of claim 13 , wherein the first wring is a power supply line configured to carry a first potential for supplying the initialization voltage to the capacitor and a second potential higher than the first potential for driving the electro-optic element.

17. The display device of claim 5 , wherein the first wiring is parallel to the scanning line.

18. The display device of claim 9 , wherein the first wiring is parallel to the scanning line.

Priority Claims (1)
JP 2008-006735 · Jan 16, 2008 · national
Continuity (3)
Continuation 13767899 · Feb 15, 2013
Continuation 12314315 · Dec 8, 2008
Related Publication 20140361962A1 · Dec 11, 2014