System and method for processing potentially self-inconsistent memory transactions
A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
1. A method comprising:
providing, from a processor, a memory request and a first coherency state value for a coherency granule associated with the memory request;
providing, from the processor, a select one of a first indicator or a second indicator in response to determining whether the first coherency state value represents a combined coherency state for a plurality of caches of the processor, the first indicator identifying the first coherency state value as representing a cumulative coherency state and the second indicator identifying the first coherency state value as representing a potentially non-cumulative coherency state;
receiving, at the processor, a request for the combined coherency state for the coherency granule in response to providing the second indicator;
determining a second coherency state value for the coherency granule in response to the request, the second coherency state value representing the combined coherency state for the coherency granule for the processor:
providing the second coherency state value and the first indicator in response to determining the second coherency state value;
wherein determining the second coherency state value further comprises;
snooping each cache of the plurality of caches to determine a plurality of cache coherency states values, each cache coherency state value representing a coherency state of the coherency granule of a corresponding cache; and
selecting the second coherency state value from the plurality of cache coherency state values.
2. The method of claim 1 , wherein selecting the second coherency state value from the plurality of cache coherency state values comprises selecting as the second coherency state value a cache coherency state value representing a most restrictive cache coherency state of the coherency states represented by the cache coherency state values.
3. The method of claim 2 , wherein each the cache coherency state values comprises a distinct value corresponding to a relative restrictiveness of the corresponding coherency state.
4. The method of claim 1 , further comprising:
determining whether to request the combined coherency state for the coherency granule in response to receiving the second indicator from the processor; and
providing an indicator of the request for the combined coherency state to the processor in response to determining to request the combined coherency state.
5. The method of claim 4 , further comprising:
processing the memory transaction without requesting the combined coherency state in response to determining not to request the combined coherency state.
6. The method of claim 1 , further comprising:
providing the memory request and the first coherency state value for the coherency granule to another processor in response to providing the first indicator.
7. The method of claim 1 , further comprising:
determining whether to request the particular coherency state for the first coherency granule from the processor in response to receiving the first indicator.
8. The method of claim 7 , wherein the request for the particular coherency state for the coherency granule is in response to determining to request the particular coherency state.
9. The method of claim 7 , further comprising:
providing the memory request and the first coherency state value for the coherency granule to another processor in response to determining not to request the particular coherency state.
10. The method of claim 1 , further comprising:
updating a cache coherency directory in response to providing the second coherency state value and the first indicator.
11. The method of claim 1 , wherein the cache coherency directory comprises an entry for the cache coherency granule and a plurality of processor node coherency state values.
12. The method of claim 1 , wherein the first coherency state value indicates one of a transaction error state, a shared state, a modified intervention state, a shared intervention state, a proxy intervention state, a null state, and a modified cast-out state.
13. A method comprising:
receiving, from a processor, a first memory request and a first coherency state value for a first coherency granule associated with the first memory request;
receiving, from the processor, a first indicator associated with the first coherency state value, the first indicator identifying the first coherency state value as representing a potentially non-cumulative coherency state of the first coherency granule for a plurality of caches of the processor;
determining whether to request a combined coherency state for the first coherency granule from the processor in response to receiving the first indicator;
providing a second indicator to the processor to request the combined coherency state for the first coherency granule in response to determining to request the combined coherency state for the first coherency granule;
receiving, from the processor, a second memory request and a second coherency state value for a second coherency granule associated with the second memory request;
receiving, from the processor, a second indicator associated with the second coherency state value, the second indicator identifying the second coherency state value as representing a cumulative coherency state of the second coherency granule for the plurality of caches of the processor; and
processing the second memory request for distribution in response to receiving the second indicator.
14. The method of claim 13 , further comprising:
receiving, from the processor, a third coherency state value for the first coherency granule and a third indicator associated with the second coherency state value subsequent to providing the second indicator, the third indicator identifying the third coherency state value as representing the cumulative coherency state of the first coherency granule; and
processing the first memory transaction for distribution in response to receiving the third coherency state value and the third indicator.
15. The method of claim 14 , wherein processing the first memory transaction for distribution comprises updating a cache coherency directory based on the third coherency state value.
16. The method of claim 13 , further comprising:
processing the first memory request for distribution in response to determining not to request the combined coherency state for the first coherency granule.
17. The method of claim 16 , further comprising:
providing a third indicator to the processor in response to determining not to request the combined coherency state for the first coherency granule, the third indicator indicating the combined coherency state for the first coherency granule is not to be requested from the processor.
18. A system comprising:
a transaction management module associated with a plurality of processors; and
a first processor of the plurality of processors, the first processor being coupleable to the transaction management module, the first processor comprising:
a processor core;
a plurality of caches; and
a coherency management module comprising:
a first output configured to provide a memory transaction associated with a coherency granule;
a second output configured to provide a first coherency state value for the coherency granule; and
a third output configured to provide a first indicator, the first indicator indicating whether first coherency state value represents a potentially non-cumulative coherency state for the coherency granule for the plurality of caches
wherein the transaction management module comprises:
a first input coupled to the first output of the coherency management module to receive the memory transaction;
a second input coupled to the second output of the coherency management module to receive the first coherency state value;
a third input coupled to the third output of the coherency management module to receive the first indicator; and
a first output; and
wherein the transaction management module is configured to:
determine whether to request a combined coherency state of the coherency granule from the first processor in response to the first indicator; and
provide a second indicator via the first output in response to determining to request the combined coherency state of the coherency granule from the processor, the second indicator representing a request for the combined coherency state of the coherency granule.
19. The system of claim 18 , wherein:
the first processor further comprises a first input coupled to the first output of the transaction management module; and
the first processor configured to:
determine a second coherency state value, the second coherency state value representing a cumulative coherency state of the coherency granule for the plurality of caches;
provide the second coherency state value via the second output of the coherency management module and a third indicator via the third output, the third indicator indicating that the second coherency state represents the cumulative coherency state of the coherency granule.
20. The system of claim 18 , further comprising:
a second processor coupled to the transaction management module, the second processor having a shared memory with the first processor.