Integrated thermal solutions for packaging integrated circuits
A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
1. A method comprising:
attaching a wafer on a carrier through an adhesive;
forming trenches in the carrier to convert the carrier into a heat sink; and
sawing the heat sink, the wafer, and the adhesive into a plurality of packages.
2. The method of claim 1 further comprising bonding a heat spreader to the carrier, wherein the heat spreader seals the trenches, and wherein the trenches are connected to holes in the heat spreader.
3. The method of claim 2 further comprising:
forming the holes in the heat spreader; and
connecting pipes to the trenches through the holes.
4. The method of claim 1 , wherein the wafer comprises:
a semiconductor substrate; and
active devices at a surface of the semiconductor substrate, wherein the method further comprises, before the steps of forming the trenches and sawing, grinding the semiconductor substrate.
5. The method of claim 1 , wherein the wafer comprises:
a substrate; and
through vias in the substrate, wherein the method further comprises, before the steps of forming the trenches and sawing, grinding the substrate, and forming redistribution lines connecting to the through vias.
6. The method of claim 1 , wherein the heat sink, the carrier, and the adhesive are sawed in a same sawing step.
7. The method of claim 1 , wherein the wafer comprises an additional wafer therein, wherein the additional wafer comprises a first substrate, and a plurality of vias extending from a top surface of the first substrate into the first substrate, wherein the method further comprises bonding a plurality of dies over the additional wafer, wherein each of the plurality of dies comprises a second substrate, and wherein the carrier is bonded to top surfaces of the second substrates of the plurality of dies.
8. A method comprising:
attaching a semiconductor wafer to a carrier through an adhesive;
after the step of attaching, forming conductive features on the semiconductor wafer, wherein the conductive features are electrically coupled to devices in the semiconductor wafer;
after the step of forming the conductive features, forming trenches in the carrier to convert the carrier into a heat sink; and
sawing the heat sink, the semiconductor wafer, and the adhesive into a plurality of packages.
9. The method of claim 8 further comprising, after the step of attaching and before the step of forming the conductive features, grinding a semiconductor substrate of the semiconductor wafer.
10. The method of claim 8 , wherein at a time the step of sawing is performed, the trenches are not filled.
11. The method of claim 8 , wherein the semiconductor wafer comprises a silicon wafer, and wherein the silicon wafer is substantially free from integrated circuit devices therein.
12. The method of claim 8 further comprising:
sealing the trenches to form micro-channels; and
connecting pipes to the micro-channels.
13. The method of claim 8 , wherein the step of forming the trenches comprises forming a first plurality of trenches parallel to each other.
14. The method of claim 13 , wherein the step of forming the trenches further comprises forming a second plurality of trenches parallel to each other and perpendicular to the first plurality of trenches, and wherein the first and the second plurality of trenches are interconnected.
15. A method comprising:
attaching a wafer to a carrier through an adhesive;
after the step of attaching, thinning the wafer;
after the step of thinning, forming trenches in the carrier to convert the carrier into a heat sink; and
sawing the heat sink, the wafer, and the adhesive into a plurality of packages.
16. The method of claim 15 , wherein the wafer comprises through vias in a substrate of the wafer, and wherein the step of thinning comprises thinning the substrate to expose the through vias, and wherein the method further comprises forming conductive features connecting to the through vias.
17. The method of claim 15 , wherein at a time the step of sawing is performed, the trenches are not filled.
18. The method of claim 15 , wherein the wafer comprises a silicon wafer, and wherein the silicon wafer is substantially free from integrated circuit devices therein.
19. The method of claim 15 further comprising:
sealing the trenches to form micro-channels; and
connecting pipes to the micro-channels.
20. The method of claim 15 , wherein the step of forming the trenches comprises:
forming a first plurality of trenches parallel to each other; and
forming a second plurality of trenches parallel to each other and perpendicular to the first plurality of trenches, and wherein the first and the second plurality of trenches are interconnected.