Resurf high voltage diode
A trench-isolated RESURF diode structure ( 100 ) is provided which includes a substrate ( 150 ) in which is formed anode ( 130, 132 ) and cathode ( 131 ) contact regions separated from one another by a shallow trench isolation region ( 114, 115 ), along with a buried cathode extension region ( 104 ) formed under a RESURF anode extension region ( 106, 107 ) such that the cathode extension region ( 104 ) extends beyond the cathode contact ( 131 ) to be sandwiched between upper and lower regions ( 103, 106, 107 ) of opposite conductivity type.
1. A method of fabricating a high voltage semiconductor diode device, comprising in any order:
forming a heavily doped second terminal contact region of a second conductivity type in a semiconductor substrate region;
forming a second terminal extension region of the second conductivity type in the semiconductor substrate region with an upper portion around the heavily doped second terminal contact region, where the second terminal extension region comprises a buried RESURF extension region that extends laterally past the heavily doped second terminal contact region;
forming a heavily doped first terminal contact region of a first conductivity type in a first terminal contact area of the semiconductor substrate region to be spaced apart from the heavily doped second terminal contact region; and
forming a first terminal extension region of the first conductivity type in the semiconductor substrate region around the heavily doped first terminal contact region, the first terminal extension region located above the buried RESURF extension region and extending part way toward the heavily doped second terminal contact region without reaching the heavily doped second terminal contact region, thereby forming a lateral p-n junction at the surface of the semiconductor substrate region between the first terminal extension region and the upper portion of the second terminal extension region at a lateral spacing distance from the heavily doped second terminal contact region and below a shallow trench isolation region formed on a surface of the semiconductor substrate region, where the buried RESURF extension region extends laterally beyond the heavily doped first terminal contact region without reaching a deep trench isolation region.
2. The method of claim 1 , where the second terminal extension region is surrounded by the first terminal extension region and a semiconductor region of the first conductivity type from at least the top and the bottom.
3. The method of claim 1 , where forming the semiconductor substrate region comprises forming the semiconductor substrate region within an isolation structure comprising the deep trench isolation region formed to surround the semiconductor substrate region, a buried insulator layer formed at the bottom of the semiconductor substrate region, and the shallow trench isolation region formed on the surface of the semiconductor substrate region.
4. The method of claim 1 , where forming the first terminal extension region comprises implanting the first terminal extension region with an implant mask so that the first terminal extension region is separated from the heavily doped second terminal contact region by a first lateral spacing dimension that is controlled to maximize breakdown voltage for the semiconductor device.
5. The method of claim 2 , where forming the first terminal extension region comprises forming a p-type RESURF layer or an n-type RESURF layer, and where forming the second terminal extension region comprises forming an n-type RESURF layer or a p-type RESURF layer.
6. A method for forming a high voltage diode device, comprising:
providing a semiconductor-on-insulator substrate comprising a substrate layer formed over a buried insulator layer and surrounded by a deep trench isolation region;
forming shallow trench isolation regions on the substrate layer to define a second terminal contact opening separated from a first terminal contact opening by a first shallow trench isolation region; and then, in any order:
selectively implanting a heavily doped second terminal contact region of a second conductivity type in the substrate layer in the second terminal contact opening;
selectively implanting a second terminal extension region of the second conductivity type in the substrate layer with an upper portion around the heavily doped second terminal contact region, where the second terminal extension region comprises a buried RESURF extension region that extends laterally past the heavily doped second terminal contact region;
selectively implanting a heavily doped first terminal contact region of a first conductivity type in the first terminal contact opening of the substrate layer to be spaced apart from the heavily doped second terminal contact region; and
selectively implanting a peripheral first terminal well region of the first conductivity type in the substrate layer, where the peripheral first terminal well region extends laterally above the buried RESURF extension region of the second terminal extension region and toward the heavily doped second terminal contact region without reaching the heavily doped second terminal contact region, and wherein the peripheral first terminal well region and the upper portion of the second terminal extension region form a lateral p-n junction at a lateral spacing distance from the heavily doped second terminal contact region at the surface of the substrate layer below the first shallow trench isolation region, where the buried RESURF extension region extends laterally beyond the heavily doped first terminal contact region without reaching the deep trench isolation region.
7. The method of claim 6 , further comprising forming a conductive electrode layer on the first shallow trench isolation region which is positioned over the lateral p-n junction formed at the surface of the substrate layer.
8. The method of claim 6 , where regions formed with material of the first conductivity type are formed as p-type regions, and where regions formed with material of the second conductivity type are formed as n-type regions, respectively.
9. The method of claim 6 , where the heavily doped first terminal contact region and peripheral first terminal well region form an anode terminal or a cathode terminal, and where the heavily doped second terminal contact region and second terminal extension region form a cathode terminal or an anode terminal.