Self-aligned contact metallization for reduced contact resistance
Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.
1. A semiconductor integrated circuit, comprising:
a substrate having a number of channel regions;
a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
p-type source/drain regions in the substrate and adjacent to a corresponding channel region;
n-type source/drain regions in the substrate and adjacent to a corresponding channel region;
a p-type germanium layer on at least a portion of the p-type source/drain regions;
an n-type III-V semiconductor material layer on at least a portion of the n-type source drain regions; and
metal contacts on each of the p-type germanium layer and the n-type III-V semiconductor material layer.
2. The integrated circuit of claim 1 wherein the n-type III-V semiconductor material layer is undoped.
3. The integrated circuit of claim 1 wherein the n-type III-V semiconductor material layer has a bandgap of less than 0.5 eV.
4. The integrated circuit of claim 1 wherein the n-type III-V semiconductor material layer has a bandgap of less than 0.2 eV.
5. The integrated circuit of claim 1 wherein the n-type III-V semiconductor material layer is doped.
6. The integrated circuit of claim 5 wherein the n-type III-V semiconductor material layer is doped with one or more amphoteric dopants.
7. The integrated circuit of claim 6 wherein the n-type III-V semiconductor material layer is doped with one or more amphoteric dopants to greater than a 1E18 atoms/cm 3 substitutional concentration.
8. The integrated circuit of claim 1 wherein the p-type germanium layer is doped with boron.
9. The integrated circuit of claim 8 wherein the boron concentration is in excess of 1E20 cm ˜ 3.
10. The integrated circuit of claim 1 wherein the device is implemented with a planar transistor architecture.
11. The integrated circuit of claim 1 wherein the device is implemented with a non-planar transistor architecture.
12. The integrated circuit of claim 11 wherein the non-planar transistor architecture comprises at least one of FinFET transistors and nanowire transistors.
13. The integrated circuit of claim 1 wherein the p-type and n-type source/drain regions comprise silicon, germanium, or an alloy thereof.
14. An electronic device comprising:
a printed circuit board having one or more integrated circuits as defined in claim 1 .
15. The electronic device of claim 14 wherein the one or more integrated circuits comprise at least one of a communication chip and a processor.
16. The electronic device of claim 14 wherein the device is a computing device.
17. A device, comprising:
a silicon-containing substrate having a number of channel regions;
a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
p-type source/drain regions in the substrate and adjacent to a corresponding channel region, the p-type source/drain regions comprising silicon, germanium, or an alloy thereof;
n-type source/drain regions in the substrate and adjacent to a corresponding channel region, the n-type source/drain regions comprising silicon, germanium, or an alloy thereof;
a p-type germanium layer on at least a portion of the p-type source/drain regions;
an n-type III-V semiconductor material layer on at least a portion of the n-type source drain regions; and
metal contacts on each of the p-type germanium layer and the n-type III-V semiconductor material layer.
18. The device of claim 17 wherein the n-type III-V semiconductor material layer is undoped.
19. The device of claim 17 wherein the n-type III-V semiconductor material layer is doped.
20. The device of claim 19 wherein the n-type III-V semiconductor material layer is doped with one or more amphoteric dopants.
21. The device of claim 20 wherein the n-type III-V semiconductor material layer is doped with one or more amphoteric dopants to greater than a 1E18 atoms/cm 3 substitutional concentration.
22. The device of claim 17 wherein the n-type III-V semiconductor material layer has a bandgap of less than 0.5 eV.
23. The device of claim 17 wherein the p-type germanium layer is doped with boron.
24. The device of claim 23 wherein the boron concentration is in excess of 1E20 cm −3 .
25. A method for forming a semiconductor device, comprising:
providing a substrate having a number of channel regions;
providing a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
providing p-type source/drain regions in the substrate and adjacent to a corresponding channel region;
providing n-type source/drain regions in the substrate and adjacent to a corresponding channel region;
providing a p-type germanium layer on at least a portion of the p-type source/drain regions;
providing an n-type III-V semiconductor material layer on at least a portion of the n-type source drain regions and over the p-type source drain regions having the p-type germanium layer thereon;
etching back the n-type III-V semiconductor material layer to expose the underlying p-type germanium over the p-type source drain regions and to thin the n-type III-V semiconductor material layer over the n-type source drain regions; and
providing metal contacts on each of the p-type germanium layer and the n-type III-V semiconductor material layer.