IP Library › Granted Patent US 9,059,072
Granted Patent B2
US 9,059,072 · App. 14/294,052 · Granted Jun 16, 2015

Semiconductor packages and methods of fabricating the same

Inventors: Eun-Kyoung Choi (Gyeonggi-do, KR); SeYoung Jeong (Suwon-si, KR); Kwang-chul Choi (Suwon-si, KR); Tae Hong Min (Gumi-si, KR); Chungsun Lee (Gunpo-si, KR); Jung-Hwan Kim (Bucheon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L24/17H01L21/561H01L23/3128H01L24/97H01L2224/16225H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73215H01L2224/73253H01L2224/73265H01L2224/97H01L2924/01013H01L2924/01029H01L2924/01047H01L2924/01073H01L2924/01079H01L2924/15311H01L2924/1815H01L2924/18161H01L24/48H01L25/0657H01L25/18H01L25/50H01L2224/73257H01L2225/06517H01L2225/06589H01L2924/01005H01L2924/01006H01L2924/01019H01L2924/01024H01L2924/01033H01L2924/01068H01L2924/01074H01L2924/014H01L2225/06513H01L2225/06506H01L2225/06541H01L2225/06568H01L23/3677H01L24/16H01L24/32H01L21/6835H01L24/73H01L2224/16145H01L2224/32145H01L2224/48145H01L2221/68327H01L2221/6834H01L23/36H01L23/3672H01L2224/13025H01L23/367H01L23/5226
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Quick Facts
Patent No.
US 9,059,072
App. No.
14/294,052
Granted
Jun 16, 2015
Kind
B2
Abstract

Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Claims (11)

1. A semiconductor package stack structure comprising:

a first semiconductor chip;

a second semiconductor chip overlying the first semiconductor chip;

a planarized molding layer covering the second semiconductor chip and exposing a top surface of the second semiconductor chip, wherein a top surface of the planarized molding layer is substantially coplanar with the top surface of the second semiconductor chip; and

a heat sink layer that directly contacts the exposed top surface of the second semiconductor chip and the planarized molding layer, the heat sink layer including,

a first metal layer directly on the second semiconductor chip and the planarized molding layer; and

a second metal layer disposed on the first metal layer,

wherein the first metal layer comprises a metallic material capable of preventing a diffusion of a metallic component included in the second metal layer.

2. The package stack structure of claim 1 , wherein, in cross-sectional view, the heat sink layer extends in a straight line across the planarized molding layer and the top surface of the second semiconductor chip at an interface thereof.

3. The package stack structure of claim 1 , wherein the second semiconductor chip comprises a through via extending through at least a portion thereof, and wherein the through via is contact with the heat sink layer.

4. The package stack structure of claim 1 , further comprising a third semiconductor chip between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip is a logic device and second and third chips are memory devices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2015
From: CHOI, EUN-KYOUNG; JEONG, SEYOUNG; CHOI, KWANG-CHUL; MIN, TAE HONG; LEE, CHUNGSUN; KIM, JUNG-HWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 034881/0044 →
Priority Claims (1)
KR 10-2010-0139991 · Dec 31, 2010 · national
Continuity (2)
Division 13235372 · Sep 17, 2011
Related Publication 20140300004A1 · Oct 9, 2014