Polymer layers embedded with metal pads for heat dissipation

1. An integrated circuit structure comprising:

a metal pad;

a passivation layer comprising a portion over the metal pad;

a first polymer layer over the passivation layer;

a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer, wherein the first PPI is electrically connected to the metal pad;

a dummy metal pad in the first polymer layer;

a second polymer layer over the first polymer layer, the dummy metal pad, and the first PPI;

an Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad;

a package component comprising a surface conductive feature; and

a solder region bonded to the surface conductive feature in the package component, wherein the solder region is electrically coupled to the dummy metal pad, and wherein the dummy metal pad and the solder region are electrically floating.

2. The integrated circuit structure of claim 1 , wherein the metal pad is electrically coupled to the UBM and the dummy metal pad, wherein the integrated circuit structure is configured to have a current flowing path between the UBM and the metal pad, and wherein the integrated circuit structure is configured not to have any current flowing path between the UBM and the dummy metal pad.

3. The integrated circuit structure of claim 1 , wherein an entirety of a bottom surface of the dummy metal pad is in physical contact with a top surface of an underlying dielectric material.

4. The integrated circuit structure of claim 1 further comprising:

a third polymer layer between the first polymer layer and the second polymer layer; and

a second PPI extending into the third polymer layer, wherein the second PPI electrically couples the UBM to the dummy metal pad.

5. The integrated circuit structure of claim 1 , wherein the first polymer layer and the second polymer layer are in physical contact with each other.

6. The integrated circuit structure of claim 1 , wherein the dummy metal pad is configured to not allow current to pass through.

7. An integrated circuit structure comprising:

a semiconductor substrate;

an interconnect structure over the semiconductor substrate;

a passivation layer over the interconnect structure;

a metal pad over the interconnect structure, wherein the passivation layer covers a portion of the metal pad;

a metal pillar over and contacting the metal pad;

a first polymer layer over the passivation layer and the metal pillar;

a Post-Passivation Interconnect (PPI) comprising a via portion in the first polymer layer, and a line portion over the first polymer layer, wherein the via portion is overlying and electrically connected to the metal pillar;

a dummy metal pad in the first polymer layer;

a second polymer layer over the first polymer layer; and

an Under-Bump-Metallurgy (UBM) extending into the second polymer layer, wherein the UBM is electrically coupled to the metal pad and the dummy metal pad.

8. The integrated circuit structure of claim 7 , wherein the dummy metal pad is a terminal feature of an electrical path comprising the dummy metal pad.

9. The integrated circuit structure of claim 7 , wherein the UBM, the metal pad, and the dummy metal pad are electrically grounded.

10. The integrated circuit structure of claim 7 , wherein the UBM, the metal pad, and the dummy metal pad are electrically coupled to a positive power supply node.

11. The integrated circuit structure of claim 7 , wherein the UBM, the metal pad, and the dummy metal pad are electrically coupled to a signal voltage.

12. The integrated circuit structure of claim 7 , wherein the metal pad comprises aluminum copper, and wherein the dummy metal pad comprises copper.

13. The integrated circuit structure of claim 7 further comprising:

an additional dummy metal pad in the first polymer layer;

a package component comprising a surface conductive feature; and

a solder region bonded to the surface conductive feature in the package component, wherein the solder region is electrically coupled to the additional dummy metal pad, and wherein the dummy metal pad and the solder region are electrically floating.

14. An integrated circuit structure comprising:

a metal pad;

a passivation layer comprising a portion over the metal pad;

a first polymer layer over the passivation layer;

a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer, wherein the first PPI is electrically connected to the metal pad;

a dummy metal pad in the first polymer layer, wherein all sidewalls and all bottom surfaces of the dummy metal pad are in contact with dielectric materials;

a second polymer layer over the first polymer layer, the dummy metal pad, and the first PPI; and

an Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad and the metal pad, and wherein the dummy metal pad comprises no additional electrical connection besides an electrical connection to the UBM.

15. The integrated circuit structure of claim 14 , wherein the integrated circuit structure is configured not to have any current flowing between the UBM and the dummy metal pad.

16. The integrated circuit structure of claim 14 further comprising a transistor electrically coupled to the metal pad.

17. The integrated circuit structure of claim 14 , wherein the UBM, the metal pad, and the dummy metal pad are electrically coupled to a positive power supply node.

18. The integrated circuit structure of claim 14 , wherein the UBM, the metal pad, and the dummy metal pad are electrically coupled to a signal voltage.

19. The integrated circuit structure of claim 14 , wherein the metal pad comprises aluminum copper, and wherein the dummy metal pad comprises copper.

20. The integrated circuit structure of claim 14 further comprising:

an additional dummy metal pad in the first polymer layer;

a package component comprising a surface conductive feature; and

a solder region bonding the surface conductive feature to the UBM, wherein the solder region is electrically coupled to the additional dummy metal pad, and wherein the dummy metal pad and the solder region are electrically floating.