Analog transistor

1. A process for manufacturing an analog transistor comprising:

providing a doped well;

forming a screen layer that contacts and overlies at least a portion of the doped well;

forming an epitaxial undoped channel layer above the screen layer, and the undoped channel not being subjected to contaminating threshold voltage implants or halo implants;

forming a gate dielectric and gate electrode above the undoped channel and positioned between a source and a drain, the source and drain configured to respond to an analog signal; and

maintaining process conditions so that a portion of the undoped channel adjacent to the gate dielectric remains undoped in the final analog transistor.

2. The process of claim 1 , further comprising the step of forming a threshold voltage setting layer positioned between the substantially undoped channel and the screen layer.

3. The process of claim 2 , further comprising the step of counter doping the threshold voltage setting layer with respect to the screen layer.

4. The process of claim 2 , further comprising the step of forming an asymmetric threshold voltage setting layer that extends only partially between the source and the drain.

5. The process of claim 4 , wherein the threshold voltage setting layer that extends from the source to a position below the substantially undoped channel short of the drain.

6. The process of claim 2 , wherein the threshold voltage setting layer is formed by out diffusion from the screen layer into an epitaxially grown layer.

7. The process of claim 2 , wherein the threshold voltage setting layer is formed by growing an epitaxial layer on the screen layer and doping the epitaxial layer through either implantation or in-situ doping.

8. The process of claim 2 , wherein the threshold voltage setting layer is formed by delta doping to form an offset doped plane.

9. The process of claim 2 , wherein the threshold voltage setting layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.

10. The process of claim 2 , further comprising:

forming a dopant migration resistant layer above the threshold voltage setting layer.

11. The process of claim 2 , further comprising:

forming a first dopant migration resistant layer above the threshold voltage setting layer;

forming a second dopant migration resistant layer above the threshold voltage setting layer.

12. The process of claim 1 , further comprising the steps of:

forming a first channel LDD extending from the source toward the drain; and

forming a second channel LDD extending from the drain toward the source.

13. The process of claim 12 , wherein the first channel LDD extends a different distance than the second channel LDD.

14. The process of claim 12 , wherein the first channel LDD has a greater depth than the second channel LDD.

15. The process of claim 12 , wherein the first channel LDD has a greater dopant density than the second channel LDD.

16. The process of claim 1 , further comprising the step of depositing the gate metal of the gate electrode, wherein the gate metal is selected to have a work function intermediate between band edge and midgap.

17. The process of claim 1 , further comprising the step forming an electrical tap to the doped well to permit biasing that adjusts threshold voltage.

18. The process of claim 1 , wherein the screen layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.

19. The process of claim 1 , wherein the screen layer is formed by epitaxial growth subject to at least one of implantation and in situ doping.

20. The process of claim 1 , wherein the screen layer is positioned above the bottom of the source and drain.