Memory device power managers and methods
Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
1. A memory device, comprising:
a stack of memory arrays;
a logic controller on a die stacked with the stack of memory arrays; and
an activity tracker located in the logic controller to monitor different levels of activity of at least one of a plurality of portions of the stack of memory arrays, wherein the logic controller is configured to adjust a power state of the at least one portion to correspond to the level of activity of the at least one portion, wherein a power state includes powering down only selected memory vault controllers and their associated memory vaults, wherein the portions include a plurality of vertical memory vaults, and wherein each vertical memory vault is associated with a respective vault controller located on the logic die, and each vault controller includes an activity tracker;
a plurality of serialized communication link interfaces to couple the plurality of vertical memory vaults to a host processor; and
a matrix switch enabling cross-connecting each of the plurality of serialized communication link interfaces to a selected vertical memory vault.
2. The memory device of claim 1 , wherein the stack of memory arrays is a portion of a stack of memory dies.
3. The memory device of claim 1 , wherein the logic controller is configured to change a power state of one or more serialized communication link interfaces.
4. A memory device, comprising:
a stack of memory dies;
a logic die stacked with the stack of memory dies;
an activity tracker located in the logic die to monitor levels of activity of at least one portion of the stack of memory dies, wherein the logic die is configured to adjust a power state of the at least one portion to correspond to the level of activity of the at least one portion, wherein the logic die is configured to change a power state of an individual vault controller, wherein the portions include a plurality of vertical memory vaults, and wherein each vertical memory vault is associated with a respective vault controller located on the logic die, and each vault controller includes an activity tracker;
a plurality of serialized communication link interfaces to couple the plurality of vertical memory vaults to a host processor; and
a matrix switch enabling cross-connecting each of the plurality of serialized communication link interfaces to a selected vertical memory vault.
5. The memory device of claim 4 , wherein the logic die is configured to change a power state of one or more serialized communication link interfaces coupled to the vault controllers.
6. A memory device, comprising:
a stack of memory dies;
a number of originating devices; and
a logic die stacked with the stack of memory dies to interface between the stack of memory dies and the number of originating devices, wherein the logic die is configured to change a power state of a portion of the stack of memory dies to correspond to a power state of one of the number of originating devices, wherein a power state includes powering down only selected memory vault controllers and their associated memory vaults, wherein the portion includes a plurality of vertical memory vaults, and wherein each vertical memory vault is associated with a respective vault controller located on the logic die, and each vault controller includes an activity tracker;
a plurality of serialized communication link interfaces to couple the plurality of vertical memory vaults to a host processor; and
a matrix switch enabling cross-connecting each of the plurality of serialized communication link interfaces to a selected vertical memory vault.
7. The memory device of claim 6 , wherein the number of originating devices comprise a number of processors.
8. The memory device of claim 7 , wherein the number of processors comprise a number of processor cores of a multi-core processing device.
9. The memory device of claim 6 , wherein the stack of memory dies includes a number of vertical memory vaults, and the logic die is configured to change a power state of one or more vertical memory vaults.
10. The memory device of claim 9 , wherein the logic die is configured to receive a packet command from one or more of the originating devices to change the power state.
11. A method of operating a memory device, comprising:
individually controlling a number of different memory portions of a stack of memory arrays respectively using a number of memory vault controllers located in a locally attached logic die;
monitoring an activity level of a memory portion of the number of different memory portions using an activity tracker located in a corresponding memory vault controller of the memory vault controllers, wherein each vertical memory vault is associated with one respective vault controller located on the logic die, and each vault controller includes an activity tracker, wherein a plurality of serialized communication link interfaces couple the plurality of vertical memory vaults to a host processor, and wherein a matrix switch enables cross-connecting each of the plurality of serialized communication link interfaces to a selected vertical memory vault; and
adjusting a power state of one or more portions to correspond to the level of activity of the one or more portions, wherein a power state includes powering down only selected memory vault controllers and their associated memory vaults.
12. The method of claim 11 , further including comparing the activity level of the at least one of the number of different memory portions to a threshold length of time.
13. The method of claim 11 , wherein individually controlling a number of different memory portions of a stack of memory arrays includes controlling a number of different vertical memory vaults.
14. The method of claim 11 , wherein adjusting a power state of one or more portions further comprises adjusting a power state of one or more portions corresponding to a power state of one or more associated processor cores.