Scan circuit, semiconductor device, and method for testing semiconductor device
A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
1. A scan circuit comprising:
a first scan chain in which a plurality of first flip-flops are connected in series; and
a second scan chain in which a plurality of second flip-flops are connected in series, wherein
the first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and
the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
2. The scan circuit according to claim 1 , wherein
the plurality of first flip-flops are configured to output the first output data in synchronization with a first clock, and
the plurality of second flip-flops are configured to output the second output data in synchronization with a second clock.
3. The scan circuit according to claim 2 , wherein
the number of the plurality of first flip-flops is equal to the number of the plurality of second flip-flops.
4. The scan circuit according to claim 2 , wherein
the number of the plurality of first flip-flops is larger than the number of the plurality of second flip-flops by n (n is a natural number), and
the second scan chain includes n dummy flip-flops.
5. The scan circuit according to claim 2 , wherein
the first scan chain includes an auxiliary output terminal connected to the n dummy flip-flops.
6. A semiconductor device comprising:
a combinational circuit; and
a scan circuit, wherein
the scan circuit includes:
a first scan chain in which a plurality of first flip-flops are connected in series; and
a second scan chain in which a plurality of second flip-flops are connected in series,
the first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and
the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
7. The semiconductor device according to claim 6 , wherein
the plurality of first flip-flops output the first output data in synchronization with a first clock, and
the plurality of second flip-flops output the second output data in synchronization with a second clock.
8. The semiconductor device according to claim 7 , wherein
the number of the plurality of first flip-flops is equal to the number of the plurality of second flip-flops.
9. The semiconductor device according to claim 7 , wherein
the number of the plurality of first flip-flops is larger than the number of the plurality of second flip-flops by n (n is a natural number), and
the second scan chain includes n dummy flip-flops.
10. The semiconductor device according to claim 7 , wherein
the first scan chain includes an auxiliary output terminal connected to the n dummy flip-flops.
11. A method for testing a semiconductor device including a combinational circuit and a scan circuit, the scan circuit including a first scan chain in which a plurality of first flip-flops are connected in series, and a second scan chain in which a plurality of second flip-flops are connected in series, the first scan chain being configured to capture first output data of at least one of the first flip-flops of the second scan chain, the second scan chain being configured to capture second output data of at least one of the second flip-flops of the first scan chain, the method comprising:
estimating whether there is a fault in the first and second scan chains by successively inputting scan data of “0” or “1” to the first and second scan chains, respectively, and by comparing scan data output from the first and second scan chains, respectively, with an expected value; and
estimating, by using one of the scan chains in which it is estimated that there is no fault, a type of the fault and an occurrence position of the fault with respect to the other scan chain in which it is estimated that there is a fault.
12. The method for testing a semiconductor device according to claim 11 comprising
performing a mutual capture test, wherein in the mutual capture test:
scan data of “0” or “1” is set successively to the one scan chain in which it is estimated that there is no fault;
the other scan chain in which it is estimated that there is a fault captures data of the one scan chain;
the one scan chain captures data of the other scan chain; and
data output from the one scan chain is compared with an expected value.
13. The method for testing a semiconductor device according to claim 12 , comprising
performing a normal capture test,
wherein in the normal capture test:
scan data of “0” or “1” is set successively to the other scan chain in which it is estimated that there is a fault;
the one scan chain captures data of the other scan chain; and
data output from the one scan chain is compared with an expected value.
14. The method for testing a semiconductor device according to claim 12 , comprising
performing a normal capture test,
wherein in the normal capture test:
scan data that alternately changes to “0” then “1” or to “1” then “0” is set successively to the other scan chain in which it is estimated that there is a fault;
the one scan chain captures data of the other scan chain; and
data output from the one scan chain is compared with an expected value.