Executing prefix code to substitute fixed operand in subsequent fixed register instruction
For efficient issue of a superscalar instruction a circuit is employed which retrieves an instruction of each instruction code type other than a prefix based on a determination result of decoders for determining instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant. When an instruction of a target code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target code type as prefix code candidates. When an instruction of a target code type cannot be detected at the rear end of the instruction units, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.
1. A data processor operating according to an instruction set, the data processor comprising:
a plurality of general registers;
the instruction set comprising a fixed register instruction and a prefix code for modifying a subsequent fixed register instruction;
the fixed register instruction having one of the general registers implicitly assigned as an operand of the fixed register instruction without using an operand field in an instruction code of the fixed register instruction; and
when the data processor detects the fixed register instruction subsequent to the prefix code, the data processor executes a same function as that of the fixed register instruction but with another one of the general registers specified by the prefix code as the operand.
2. A data processor operating according to an instruction set, the data processor comprising:
a plurality of general registers;
the instruction set comprising a fixed register instruction and a prefix code for modifying a subsequent fixed register instruction;
the fixed register instruction having one of the general registers implicitly assigned as an operand of the fixed register instruction without using an operand field in an instruction code of the fixed register instruction; and
when the data processor detects the fixed register instruction subsequent to the prefix code, the data processor executes a same function as that of the fixed register instruction but with an immediate value specified by the prefix code as the operand.