Method for producing semiconductor device and semiconductor device
View Patent ↗A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.
1. A semiconductor device comprising a first fin-shaped semiconductor layer on a substrate;
a second fin-shaped semiconductor layer on the substrate, the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer connected to each other at their ends to form a closed loop
a first insulating film around the first fin-shaped semiconductor layer and second fin-shaped semiconductor layer;
a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer and having a width equal to a width of the first fin-shaped semiconductor layer;
a second pillar-shaped semiconductor layer on the second fin-shaped semiconductor layer and having a width equal to a width of the second fin-shaped semiconductor layer;
a first diffusion layer in an upper portion of the first fin-shaped semiconductor layer and a lower portion of the first pillar-shaped semiconductor layer;
a second diffusion layer in an upper portion of the first pillar-shaped semiconductor layer;
a third diffusion layer in an upper portion of the second fin-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer;
a fourth diffusion layer in an upper portion of the second pillar-shaped semiconductor layer;
a silicide in the upper portions of the first and third diffusion layers;
a gate insulating film around the first pillar-shaped semiconductor layer;
a first metal gate electrode around the gate insulating film;
a gate insulating film around the second pillar-shaped semiconductor layer;
a second metal gate electrode around the gate insulating film;
a metal gate line connected to the first metal gate electrode and the second metal gate electrode and extending in a direction perpendicular to a direction in which the first fin-shaped semiconductor layer and second fin-shaped semiconductor layer extend;
a contact on the upper portion of the second diffusion layer and directly connected to the second diffusion layer; and
a contact on the upper portion of the fourth diffusion layer and directly connected to the fourth diffusion layer.