Production of laterally diffused oxide semiconductor (LDMOS) device and a bipolar junction transistor (BJT) device using a semiconductor process
In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.
1. A method, comprising:
forming an epitaxial layer on a semiconductor substrate;
forming a buried region of a first conductivity type in the epitaxial layer;
forming a well region of a second conductivity type in a laterally diffused metal oxide semiconductor (LDMOS) device;
forming a reduced surface field (RESURF) oxide of the LDMOS device;
forming a well region of the first conductivity type in the LDMOS device without concurrently forming a region of the first conductivity type in a bipolar junction transistor (BJT) device;
forming, after forming the well region of the second conductivity type and after the forming the RESURF oxide, a gate oxide of the LDMOS device in contact with the RESURF oxide; and
implanting a dopant of the second conductivity type to concurrently form a drift region of the LDMOS device and a base implant region of the BJT device, the drift region having a boundary intersecting an interface between a top surface of the epitaxial layer and the gate oxide of the LDMOS device.
2. The method of claim 1 , wherein the base implant region has a depth less than a depth of the well region of the LDMOS device.
3. The method of claim 1 , wherein a depth of the drift region is the same as a depth of the base implant region.
4. The method of claim 1 , wherein the BJT device has a current gain value greater than 20.
5. The method of claim 1 , wherein the BJT device is a PNP device, the LDMOS device is an N-type LDMOS device, and the base implant region has an N-type conductivity.
6. The method of claim 1 , wherein the BJT device is an NPN device, the LDMOS device is a P-type LDMOS device, and the base implant region has a P-type conductivity.
7. The method of claim 1 , further comprising:
implanting, concurrently, the dopant to form a body region of the LDMOS device and a resistor body region of a resistor polysilicon of a resistor device.
8. The method of claim 1 , wherein the semiconductor substrate includes silicon carbide.
9. The method of claim 1 , forming, concurrently, a first silicide in the BJT device, a second silicide in the LDMOS device, and a third silicide in a resistor device.
10. The method of claim 1 , wherein the implanting of the dopant is performed within a semiconductor device including the BJT device, a complementary metal oxide semiconductor (CMOS) device, and the LDMOS device.
11. The method of claim 1 , wherein the RESURF oxide has a thickness greater than a thickness of the gate oxide.
12. A method, comprising:
forming an epitaxial layer including a buried region having a first conductivity type on a semiconductor substrate;
forming a field oxide and a well region of a second conductivity type in an LDMOS device;
forming a reduced surface field (RESURF) oxide in a laterally diffused metal oxide semiconductor (LDMOS) region of the LDMOS device after the forming the field oxide;
forming a well region of the first conductivity type in the LDMOS device without concurrently forming a region of the first conductivity type in a bipolar junction transistor (BJT) device;
forming, after forming the RESURF oxide and after the forming the field oxide, a gate oxide of the LDMOS device; and
implanting a dopant of the second conductivity type to concurrently form a drift region of the LDMOS device and a base implant region of the BJT device, the drift region having a boundary intersecting an interface between a top surface of the epitaxial layer and the gate oxide of the LDMOS device.
13. The method of claim 12 , wherein the RESURF oxide and the field oxide each have a thickness greater than a thickness of the gate oxide.
14. The method of claim 12 , wherein the field oxide is formed over the well region, and the base implant region has a depth less than a depth of the well region of the LDMOS device.
15. The method of claim 12 , wherein the base implant region has a depth greater than a depth of the well region of the LDMOS device.
16. The method of claim 12 , forming, concurrently, a first silicide in the BJT device, a second silicide in the LDMOS device, and a third silicide in a resistor device.
17. A method, comprising:
forming an epitaxial layer on a semiconductor substrate including a buried region having a first conductivity type;
forming a well region of a second conductivity type associated with a laterally diffused metal oxide semiconductor (LDMOS) device and a field oxide over at least a portion of the well region of the second conductivity type;
forming a reduced surface field (RESURF) oxide of the LDMOS device after the forming the field oxide;
forming a well region of the first conductivity type in the LDMOS device without concurrently forming a region of the first conductivity type in a bipolar junction transistor (BJT) device;
forming, after forming the RESURF oxide and after the forming the field oxide, a gate oxide of the LDMOS device; and
implanting a dopant, simultaneously, through a first portion of the RESURF oxide in a portion of the LDMOS device and through a second portion of the RESURF oxide in a portion of the BJT device.
18. The method of claim 17 , wherein the portion of the LDMOS device is a drift region of the LDMOS device that has a boundary intersecting an interface between a top surface of the epitaxial layer and the gate oxide of the LDMOS device, the portion of the BJT device is a base implant region.
19. The method of claim 17 , wherein the dopant is a first dopant,
the method further comprising:
implanting a second dopant, simultaneously, in the LDMOS device and in a portion of a resistor device.
20. The method of claim 19 , wherein the portion of the resistor device is a resistor region of a polysilicon portion of the resistor device.