Method to enable controlled side chip interconnection for 3D integrated packaging system
Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
1. A multi-die semiconductor structure, comprising:
a first main stacked dies (MSD) structure comprising a first substantially horizontal arrangement of semiconductor dies;
a second MSD structure comprising a second substantially horizontal arrangement of semiconductor dies; and
an intermediate vertical side chip (i-VSC) disposed between and electrically coupled to the first and second MSD structures.
2. The multi-die semiconductor structure of claim 1 , wherein the i-VSC is coupled to the first MSD structure via one or more front interconnections of the i-VSC, the front interconnections disposed on an active side of the i-VSC.
3. The multi-die semiconductor structure of claim 2 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via a die side pad (DSP) of the first MSD structure.
4. The multi-die semiconductor structure of claim 2 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via an end of metal routing of a die in the first MSD structure.
5. The multi-die semiconductor structure of claim 1 , wherein the i-VSC is coupled to the second MSD structure via die backside metallization (DBM) of the i-VSC.
6. The multi-die semiconductor structure of claim 5 , wherein the DBM of the i-VSC is coupled to the second MSD structure via a DSP of the second MSD structure.
7. The multi-die semiconductor structure of claim 5 , wherein the DBM of the i-VSC is coupled to the second MSD structure via an end of metal routing of a die in the second MSD structure.
8. The multi-die semiconductor structure of claim 1 , wherein the i-VSC electrically couples the first and second MSD structures via one or more through silicon vias (TSVs) of the i-VSC.
9. The multi-die semiconductor structure of claim 1 , wherein the i-VSC is coupled to the first MSD structure via one or more front interconnections of the i-VSC and a DSP of the first MSD structure, the i-VSC is coupled to the second MSD structure via DBM of the i-VSC and a DSP of the second MSD structure, and the i-VSC electrically couples the first and second MSD structures via one or more through silicon vias (TSVs) of the i-VSC.
10. A semiconductor package, comprising:
a substrate;
a first main stacked dies (MSD) structure comprising a first substantially horizontal arrangement of semiconductor dies interconnected to the substrate;
a second MSD structure comprising a second substantially horizontal arrangement of semiconductor dies interconnected to the substrate;
an intermediate vertical side chip (i-VSC) disposed between and electrically coupled to the first and second MSD structures, the i-VSC interconnected to the substrate; and
an underfill material disposed between the substrate and the first and second MSD structures, and between the substrate and the i-VSC.
11. The semiconductor package of claim 10 , wherein the i-VSC is interconnected to the substrate via a die side pad (DSP) of the i-VSC.
12. The semiconductor package of claim 10 , wherein the i-VSC is coupled to the first MSD structure via one or more front interconnections of the i-VSC, the front interconnections disposed on an active side of the i-VSC.
13. The semiconductor package of claim 12 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via a DSP of the first MSD structure.
14. The semiconductor package of claim 12 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via an end of metal routing of a die in the first MSD structure.
15. The semiconductor package of claim 10 , wherein the i-VSC is coupled to the second MSD structure via die backside metallization (DBM) of the i-VSC.
16. The semiconductor package of claim 15 , wherein the DBM of the i-VSC is coupled to the second MSD structure via a DSP of the second MSD structure.
17. The semiconductor package of claim 15 , wherein the DBM of the i-VSC is coupled to the second MSD structure via an end of metal routing of a die in the second MSD structure.
18. The semiconductor package of claim 10 , wherein the i-VSC electrically couples the first and second MSD structures via one or more through silicon vias (TSVs) of the i-VSC.
19. The semiconductor package of claim 10 , wherein the i-VSC is coupled to the first MSD structure via one or more front interconnections of the i-VSC and a DSP of the first MSD structure, the i-VSC is coupled to the second MSD structure via DBM of the i-VSC and a DSP of the second MSD structure, and the i-VSC electrically couples the first and second MSD structures via one or more through silicon vias (TSVs) of the i-VSC.
20. A semiconductor package, comprising:
a substrate;
a first main stacked dies (MSD) structure comprising a first substantially horizontal arrangement of semiconductor dies interconnected to the substrate;
a second MSD structure comprising a second substantially horizontal arrangement of semiconductor dies interconnected to the substrate;
an intermediate vertical side chip (i-VSC) disposed between and electrically coupled to the first and second MSD structures, the i-VSC interconnected to the substrate;
one or more vertical side chips (VSCs) disposed adjacent to and electrically coupled to one or both of the first and second MSD structures, but not interconnected to the substrate; and
an underfill material disposed between the substrate and the first and second MSD structures, between the substrate and the i-VSC, and between the substrate and the one or more VSCs.
21. The semiconductor package of claim 20 , wherein the one or more VSCs comprises three VSCs coupled to the first MSD structure but not the second MSD structure, and comprises three VSCs coupled to the second MSD structure but not the first MSD structure.
22. The semiconductor package of claim 20 , wherein the one or more VSCs comprises one VSC coupled to the first MSD structure but not the second MSD structure, comprises one VSC coupled to the second MSD structure but not the first MSD structure, and comprises two VSCs each coupled to both the first and second MSD structures.
23. The semiconductor package of claim 20 , wherein the i-VSC is interconnected to the substrate via a die side pad (DSP) of the i-VSC.
24. The semiconductor package of claim 20 , wherein the i-VSC is coupled to the first MSD structure via one or more front interconnections of the i-VSC, the front interconnections disposed on an active side of the i-VSC.
25. The semiconductor package of claim 24 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via a DSP of the first MSD structure.
26. The semiconductor package of claim 24 , wherein a front interconnection of the i-VSC is coupled to the first MSD structure via an end of metal routing of a die in the first MSD structure.
27. The semiconductor package of claim 20 , wherein the i-VSC is coupled to the second MSD structure via die backside metallization (DBM) of the i-VSC.
28. The semiconductor package of claim 27 , wherein the DBM of the i-VSC is coupled to the second MSD structure via a DSP of the second MSD structure.
29. The semiconductor package of claim 27 , wherein the DBM of the i-VSC is coupled to the second MSD structure via an end of metal routing of a die in the second MSD structure.
30. The semiconductor package of claim 20 , wherein the i-VSC electrically couples the first and second MSD structures via one or more through silicon vias (TSVs) of the i-VSC.