Transistors having features which preclude straight-line lateral conductive paths from a channel region to a source/drain region
Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.
1. A transistor comprising:
a channel region under a gate;
a source/drain region laterally spaced from the channel region by an active region;
one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region; and
wherein the dielectric features are configured as spaced-apart interlocking structures.
2. A transistor comprising:
a channel region under a gate;
a source/drain region laterally spaced from the channel region by an active region;
one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region; and
wherein the source/drain region is a first source/drain region on one side of the gate, and further comprising a second source/drain region on an opposing side of the gate from said first source/drain region; wherein the active region is a first active region on one side of the gate, and further comprising a second active region on an opposing side of the gate from the first active region, wherein the dielectric features are first dielectric features within the first active region, and further comprising second dielectric features within the second active region.
3. The transistor of claim 2 wherein the second dielectric features within the second active region mirror the first dielectric features within the first active region.
4. The transistor of claim 2 wherein the second dielectric features within the second active region do not mirror the first dielectric features within the first active region.
5. A transistor comprising:
a channel region under a gate;
a source/drain region laterally spaced from the channel region by an active region;
multiple spaced-apart dielectric features corresponding to dielectric islands extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region; and
wherein the source/drain region is a first source/drain region on one side of the gate, and further comprising a second source/drain region on an opposing side of the gate from said first source/drain region; wherein the active region is a first active region on one side of the gate, and further comprising a second active region on an opposing side of the gate from the first active region, wherein the dielectric features are first dielectric features within the first active region, and further comprising second dielectric features within the second active region.
6. The transistor of claim 5 wherein the second dielectric features within the second active region mirror the first dielectric features within the first active region.
7. The transistor of claim 5 wherein the second dielectric features within the second active region do not mirror the first dielectric features within the first active region.
8. A transistor comprising:
a channel region under a gate;
a source/drain region laterally spaced from the channel region by an active region; and
interlocking multi-branched dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region.
9. The transistor of claim 8 being a high-voltage transistor.
10. The transistor of claim 8 wherein the source/drain region is a first source/drain region on one side of the gate, and further comprising a second source/drain region on an opposing side of the gate from said first source/drain region; wherein the active region is a first active region on one side of the gate, and further comprising a second active region on an opposing side of the gate from the first active region, wherein the dielectric features are first dielectric features within the first active region, and wherein there are no dielectric features within the second active region.
11. The transistor of claim 8 wherein the source/drain region is a first source/drain region on one side of the gate, and further comprising a second source/drain region on an opposing side of the gate from said first source/drain region; wherein the active region is a first active region on one side of the gate, and further comprising a second active region on an opposing side of the gate from the first active region, wherein the dielectric features are first dielectric features within the first active region, and further comprising second dielectric features within the second active region.
12. The transistor of claim 11 wherein the second dielectric features within the second active region mirror the first dielectric features within the first active region.
13. The transistor of claim 11 wherein the second dielectric features within the second active region do not mirror the first dielectric features within the first active region.