Silicon carbide semiconductor device
A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 16 cm −3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
1. A method for manufacturing a silicon carbide semiconductor device comprising the steps of:
preparing a substrate made of silicon carbide having a hexagonal crystal structure and having a main surface;
forming a silicon carbide layer of a first conductivity type on said main surface of said substrate;
forming a body region of a second conductivity type having an impurity density of 5×10 16 cm −3 or greater at said silicon carbide layer;
forming a trench having a side wall inclined relative to said main surface to extend through said body region using a thermal etching;
forming a gate insulating film on said side wall of said trench; and
forming a gate electrode on said gate insulating film such that said gate electrode has a threshold voltage which allows a weak inversion layer to be formed in said body region, said threshold voltage being 2 V or greater in a temperature range of not less than a room temperature and not more than 100° C. and such that channel mobility of electrons is 30 cm 2 /Vs or greater at a room temperature.
2. The method according to claim 1 , wherein said step of forming said trench includes steps of forming a recess having vertical walls substantially perpendicular to said main surface and performing said thermal etching to incline said side wall after forming said recess.
3. The method according to claim 1 , wherein said side wall corresponds to a plane of a carbon plane side of a silicon carbide constituting said substrate.
4. The method according to claim 1 , wherein said body region has an impurity density of 1×10 20 cm −3 or smaller.
5. The method according to claim 1 , wherein said gate electrode is made of polysilicon having said first conductivity type.
6. The method according to claim 1 , wherein said gate electrode is made of n type polysilicon.
7. The method according to claim 1 , wherein said gate insulating film has a thickness of not less than 25 nm and not more than 70 nm.
8. The method according to claim 1 , wherein said second conductivity type is p type and said first conductivity type is n type.
9. The method according to claim 8 , wherein said body region has an impurity density of not less than 8×10 16 cm −3 and not more than 3×10 18 cm −3 .
10. The method according to claim 1 , wherein said threshold voltage is 3 V or greater at 100° C.
11. The method according to claim 1 , wherein said threshold voltage is 1 V or greater at 200° C.
12. The method according to claim 1 , wherein said threshold voltage has a temperature dependency of −10 mV/° C. or greater.
13. The method according to claim 1 , wherein said channel mobility of electrons is 50 cm 2 /Vs or greater at 100° C.
14. The method according to claim 1 , wherein said channel mobility of electrons is 40 cm 2 /Vs or greater at 150° C.
15. The method according to claim 1 , wherein said channel mobility of electrons has a temperature dependency of −0.3 cm 2 /Vs° C. or greater.
16. The method according to claim 1 , wherein a barrier height at an interface between said silicon carbide layer and said gate insulating film is not less than 2.2 eV and not more than 2.6 eV.
17. The method according to claim 1 , wherein:
a breakdown voltage holding layer is formed between said body region and said substrate, and
in an ON state, a channel resistance, which is a resistance value of a channel region formed in said body region, is smaller than a drift resistance, which is a resistance value in said breakdown voltage holding layer.
18. The method according to claim 1 , wherein
said step of forming said silicon carbide layer includes a step of forming said silicon carbide layer to have an impurity concentration of not less than 5×10 15 cm −3 and not more than 5×10 16 cm −3 .
19. The method according to claim 2 , wherein
said step of forming said recess includes steps of forming a patterned mask layer on said silicon carbide layer and selectively etching said body region and said silicon carbide layer to form said recess using said mask layer.
20. The method according to claim 1 , wherein
said thermal etching is performed to exhibit a predetermined crystal plane on said side wall of said trench.
21. The method according to claim 1 , wherein
said thermal etching is performed at a heat treatment temperature of not less than 700° C. and not more than 1000° C. using a mixed gas of oxygen gas and chlorine gas as the reaction gas.
22. The method according to claim 21 , wherein
a flow rate ratio of said chlorine gas to said oxygen gas is not less than 0.5 and not more than 4.0.
23. The method according to claim 1 , wherein
said side wall is inclined at an angle of not less than 50 degrees and not more than 65 degrees relative to said main surface.