Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.
1. A method of forming a transistor device, comprising:
forming a sacrificial gate structure above a semiconductor substrate;
forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of said sacrificial gate structure;
forming a tensile-stressed layer of insulating material adjacent said sidewall spacers;
performing at least one etching process to remove said sacrificial gate structure and thereby define a replacement gate cavity positioned between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity;
forming a tensile-stressed gate cap layer above said replacement gate structure and within said replacement gate cavity; and
after forming said tensile-stressed gate cap layer, removing said tensile-stressed layer of insulating material.
2. The method of claim 1 , further comprising:
after removing said tensile-stressed layer of insulating material, forming another layer of insulating material adjacent said sidewall spacers; and
forming a conductive contact structure in said another layer of insulating material that is conductively coupled to a source/drain region of said device.
3. The method of claim 1 , wherein forming said tensile-stressed gate cap layer comprises forming said tensile-stressed gate cap layer such that it has a tensile stress that is greater in magnitude than a tensile stress in said tensile-stressed layer of insulating material.
4. The method of claim 1 , wherein forming said tensile-stressed gate cap layer above said replacement gate structure and within said replacement gate cavity comprises:
depositing a tensile-stressed layer of gate cap material above said replacement gate structure within said replacement gate cavity and above said tensile-stressed layer of insulating material; and
performing a chemical mechanical polishing process to remove said tensile-stressed layer of gate cap material positioned outside of said replacement gate cavity.
5. The method of claim 1 , wherein said device is one of a FinFET transistor device or a planar transistor device.
6. The method of claim 1 , wherein forming said tensile-stressed layer of insulating material comprises forming said tensile-stressed layer of insulating material such that it has a tensile stress of at least 500 MPa.
7. The method of claim 6 , wherein forming said tensile-stressed gate cap layer comprises forming said tensile-stressed gate cap layer such that it has a tensile stress of at least 1 GPa.
8. The method of claim 1 , wherein removing said replacement gate structure causes an outward deflection of at least a portion of said sidewall spacers.
9. The method of claim 8 , wherein removing said tensile-stressed layer of insulating material causes an inward deflection of at least a portion of said sidewall spacers.
10. A method of forming a transistor device, comprising:
forming a sacrificial gate structure above a semiconductor substrate;
forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of said sacrificial gate structure;
forming a tensile-stressed layer of insulating material adjacent said sidewall spacers, said tensile-stressed layer of insulating material having tensile stress of at least 500 MPa;
performing at least one etching process to remove said sacrificial gate structure and thereby define a replacement gate cavity positioned between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity;
forming a tensile-stressed gate cap layer above said replacement gate structure and within said replacement gate cavity, wherein said tensile-stressed gate cap layer has a tensile stress of at least 1 GPa;
after forming said tensile-stressed gate cap layer, removing said tensile-stressed layer of insulating material;
after removing said tensile-stressed layer of insulating material, forming another layer of insulating material adjacent said sidewall spacers; and
forming a conductive contact structure in said another layer of insulating material that is conductively coupled to a source/drain region of said device.
11. The method of claim 10 , wherein forming said tensile-stressed gate cap layer above said replacement gate structure and within said replacement gate cavity comprises:
depositing a tensile-stressed layer of gate cap material above said replacement gate structure within said replacement gate cavity and above said tensile-stressed layer of insulating material; and
performing a chemical mechanical polishing process to remove said tensile-stressed layer of gate cap material positioned outside of said replacement gate cavity.
12. The method of claim 10 , wherein removing said replacement gate structure causes an outward deflection of at least a portion of said sidewall spacers.
13. The method of claim 12 , wherein removing said tensile-stressed layer of insulating material causes an inward deflection of at least a portion of said sidewall spacers.
14. A device, comprising:
first and second spaced-apart gate structures positioned above a surface of a semiconductor substrate;
first and second dielectric gate cap layers positioned above said first and second spaced-apart gate structures, respectively, each of said first and second dielectric gate cap layers having a tapered cross-sectional configuration wherein a width of the dielectric gate cap layer at an upper surface of the dielectric gate cap layer is less than a width of the dielectric gate cap layer at a bottom surface of the dielectric gate cap layer;
sidewall spacers positioned adjacent opposite sides of each of said first and second spaced-apart gate structures and said first and second dielectric gate cap layers, wherein facing sidewall spacers on said first and second spaced-apart gate structures define a space therebetween having a top width at a level corresponding a height of said upper surfaces of said first and second dielectric gate cap layers that is wider than a bottom width of said space at a bottom of said space; and
a conductive contact positioned in said space between said facing sidewall spacers on said first and second spaced-apart gate structures.
15. The device of claim 14 , wherein said device is one of a FinFET transistor device or a planar transistor device.
16. The device of claim 14 , wherein said first and second dielectric gate cap layers each have a tensile stress of at least 1 GPa.
17. The device of claim 14 , wherein each of said first and second dielectric gate cap layers comprise silicon nitride.
18. The device of claim 14 , wherein said conductive contact is a self-aligned contact that directly contacts at least one of said first and second dielectric gate cap layers and a facing sidewall spacer positioned adjacent at least one of said respective first and second spaced-apart gate structures.
19. The device of claim 14 , wherein said top width of said space between said first and second spaced-apart gate structures is approximately 10-30% wider than said bottom width of said space between said first and second spaced-apart gate structures.
20. The device of claim 14 , wherein each of said first and second spaced-apart gate structures is an HK/MG gate structure comprising a high-k gate insulation layer and at least one work function adjusting metal layer positioned above said high-k gate insulation layer.