IP Library Granted Patent US 9,201,705
Granted Patent B2
US 9,201,705 · App. 14/247,783 · Granted Dec 1, 2015

Multi-partitioning of memories

Inventors: Danilo Caraccio (Buonalbergo, IT); Emanuele Confalonieri (Lesmo, IT); Federico Tiziani (Muggio, IT)
Assignee: Micron Technology, Inc.
G06F9/5077G06F3/0607G06F3/0637G06F3/0644G06F3/0685G06F12/0223G06F12/0238G06F12/0246G06F13/385G11C14/009G06F2212/2022G06F2212/2024G06F2213/3804G06F2213/3854G11C13/0002G11C13/0004Y02B60/1225Y02B60/1228Y02B60/1235
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Quick Facts
Patent No.
US 9,201,705
App. No.
14/247,783
Granted
Dec 1, 2015
Kind
B2
Abstract

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Claims (33)

1. A method, comprising:

managing commands through a first interface controller to mapped portions of a first type of non-volatile memory;

mapping portions of a second type of non-volatile memory through a second interface controller; and

configuring the first interface controller to be aware of the existence of the second interface controller.

2. The method of claim 1 , further comprising coupling the first interface controller in parallel with the second interface controller.

3. The method of claim 1 , further comprising coupling the first interface controller in series with the second interface controller.

4. The method of claim 1 , further comprising configuring the first type of non-volatile memory to not have an attribute enhanced set.

5. The method of claim 4 , further comprising, based on a request from a host, configuring, by the first interface controller, portions of the first memory to include the attribute enhanced set.

6. The method of claim 1 , further comprising configuring the second type of non-volatile memory to have an attribute enhanced set.

7. The method of claim 1 , further comprising configuring the second interface controller not to be aware of the first interface controller.

8. The method of claim 1 , further comprising executing state transitions to reach an inactive state during a power management mode in at least one of the first interface controller and the second interface controller.

9. The method of claim 1 , further comprising:

inhibiting responses to a host from the second interface controller; and

generating the responses to the host from the first interface controller.

10. The method of claim 1 , further comprising abstracting the type of memory used for the first type of non-volatile memory and the second type of non-volatile memory from a host that is controlling the first interface controller and the second interface controller.

11. The method of claim 1 , further comprising managing areas of the first type of non-volatile memory where attributes are not set through the first interface controller.

12. The method of claim 1 , further comprising tracking memory partitions that are enabled to map the memory partitions.

13. The method of claim 12 , further comprising storing indications of the tracking within each of the first interface controller and the second interface controller.

14. The method of claim 1 , wherein each of the first interface controller and the second first interface controller is configured to disable selected actions during execution of commands.

15. The method of claim 1 , further comprising servicing all requests for data received from a host through the first memory controller.

16. The method of claim 1 , further comprising providing responses to a host from the second interface controller when the first interface controller is in a power saving mode and requests have been sent from the host to the first interface controller.

17. A method, comprising:

managing commands through a first interface controller to mapped portions of a first non-volatile memory, the first memory not including an attribute enhanced set; and

managing commands through a second interface controller to mapped portions of a second non-volatile memory, the second memory including an attribute enhanced set.

18. The method of claim 17 , further comprising:

configuring the first interface controller to be aware of the second interface controller; and

configuring the second interface controller not to be aware of the first interface controller.

19. A method, comprising:

managing commands through a first interface controller to mapped portions of a first memory without an attribute enhanced set, the first memory comprising NAND flash; and

mapping portions of a second memory with the attribute enhanced set through a second interface controller, the second memory comprising Phase-Change Memory (PCM), the first memory and the second memory forming portions of an embedded multi-media card (e-MMC) device.

20. The method of claim 19 , further comprising:

executing state transitions to reach an inactive state during a power management mode in both the first interface controller and the second interface controller; and

providing a reply to a host from only the first interface controller.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2014
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032736/0272 →
Continuity (3)
Continuation 13620980 · Sep 15, 2012
Continuation 12628152 · Nov 30, 2009
Related Publication 20140223087A1 · Aug 7, 2014