Method and apparatus to perform concurrent read and write memory operations
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array.
1. A method comprising:
suspending calculation of an error correction code (ECC) in response to receiving a read request to read contents of a memory array;
while writing to a second portion of the memory array, determining contents of a first portion of the memory array based on stored ECC calculated from the contents of the memory array; and
subsequently resuming calculation of the ECC.
2. The method of claim 1 , wherein determining the contents of the first portion is further based on contents of portions of the memory array that correspond to the first portion of the memory array.
3. The method of claim 2 , wherein the contents of the first portion of the memory array are not used in determining the contents of the first portion.
4. The method of claim 2 , further comprising:
reading in parallel, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
5. The method of claim 2 , further comprising:
reading in series, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
6. The method of claim 1 , wherein writing to the second portion of the memory array is in response to an internal operation initiated by a memory comprising the memory array.
7. The method of claim 1 , wherein the first portion and the second portion of the memory array share a group of sense amplifiers.
8. The method of claim 1 , wherein the contents of the memory array comprise the stored ECC.
9. A memory microcontroller comprising:
an interface to connect to a memory array; and
electronic circuitry to:
suspend calculation of an error correction code (ECC) in response to receiving a read request to read contents of the memory array;
while writing to a second portion of the memory array, determine contents of a first portion of the memory array based on stored ECC calculated from the contents of the memory array; and
subsequently resume calculating the ECC.
10. The memory microcontroller of claim 9 , wherein determining the contents of the first portion is further based on contents of portions of the memory array that correspond to the first portion of the memory array.
11. The memory microcontroller of claim 10 , wherein the contents of the first portion of the memory array are not used in determining the contents of the first portion.
12. The memory microcontroller of claim 10 , further comprising a circuit to:
read in parallel, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
13. The memory microcontroller of claim 10 , further comprising a circuit to:
read in series, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
14. The memory microcontroller of claim 9 , wherein the first portion and the second portion of the memory array share a sense amplifier.
15. The memory microcontroller of claim 9 , wherein the contents of the memory array comprise the stored ECC.
16. A system comprising:
a memory device comprising a memory, the memory device further comprising a memory microcontroller to:
suspend calculation of an error correction code (ECC) in response to receiving a read request to read contents of a memory array;
while writing to a second portion of the memory array, determine contents of a first portion of the memory array of the memory based on stored ECC calculated from the contents of the memory array; and
subsequently resume calculating the ECC; and
a processor to host one or more applications and to initiate the read request to the memory microcontroller to provide access to the memory array.
17. The system of claim 16 , wherein determining the contents of the first portion is further based on contents of portions of the memory array that correspond to the first portion of the memory array.
18. The system of claim 17 , wherein the contents of the first portion of the memory array are not used in determining the contents of the first portion.
19. The system of claim 17 , further comprising a circuit to:
read in parallel, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
20. The system of claim 17 , further comprising a circuit to:
read in series, via a bus, the contents of the portions of the memory array that correspond to the first portion of the memory array while determining the contents of the first portion.
21. The system of claim 16 , wherein the first portion and the second portion of the memory array share a sense amplifier.
22. The system of claim 16 , wherein the contents of the memory array comprise the stored ECC.