Thermal management circuit board for stacked semiconductor chip device
A method of assembling a semiconductor chip device is provided. The method includes providing a first circuit board that has a plurality of thermally conductive vias. A second circuit board is mounted on the first circuit board over and in thermal contact with the thermally conductive vias. The second circuit board includes first side facing the first circuit board and a second and opposite side.
1. A method of assembling a semiconductor chip device, comprising:
providing a first circuit board including a plurality of thermally conductive vias;
mounting a second circuit board on the first circuit board over and in thermal contact with the thermally conductive vias, the second circuit board including first side facing the first circuit board and a second and opposite side; and
coupling a first semiconductor chip on the first side of the second circuit board over and in thermal contact with the thermally conductive vias, at least a portion of the first semiconductor chip extending beyond the first side of the second circuit board.
2. The method of claim 1 , comprising placing an underfill material between and in thermal contact with the second circuit board and at least some of the thermally conductive vias.
3. The method of claim 2 , wherein the underfill material includes thermally conductive particles proximate at least some of the thermally conductive vias.
4. The method of claim 1 , wherein the first circuit board includes an opening, the thermally conductive vias being arranged around a perimeter of the opening.
5. The method of claim 4 , wherein at least a portion of the first semiconductor chip is positioned in the opening.
6. The method of claim 4 , comprising coupling a heat sink to the first semiconductor chip, at least a portion of one or both of the first semiconductor chip and the heat sink being positioned in the opening.
7. The method of claim 1 , comprising coupling a first semiconductor chip to the first side of the second circuit board over and in thermal contact with the thermally conductive vias, and a second semiconductor chip to the second side of the second circuit board.
8. The method of claim 1 , wherein the first circuit board comprises a first plurality of patterned metal lines coupled to first ends of the thermally conductive vias and a second plurality of patterned metal lines coupled to second ends of the thermally conductive vias.
9. The method of claim 1 , wherein the thermally conductive vias are electrically non-functional.
10. A method of manufacturing, comprising:
fabricating a plurality of thermally conductive vias in a first circuit board;
mounting a second circuit board on the first circuit board over and in thermal contact with the thermally conductive vias, the second circuit board including first side facing the first circuit board and a second and opposite side; and
coupling a first semiconductor chip on the first side of the second circuit board over and in thermal contact with the thermally conductive vias, at least a portion of the first semiconductor chip extending beyond the first side of the second circuit board.
11. The method of claim 10 , comprising placing an underfill material between and in thermal contact with the second circuit board and at least some of the thermally conductive vias.
12. The method of claim 11 , wherein the underfill material includes thermally conductive particles proximate at least some of the thermally conductive vias.
13. The method of claim 10 , comprising fabricating an opening in the first circuit board and arranging the thermally conductive vias around a perimeter of the opening.
14. The method of claim 13 , wherein at least a portion of the first semiconductor chip is positioned in the opening.
15. The method of claim 13 , comprising coupling a heat sink to the first semiconductor chip, at least a portion of one or both of the first semiconductor chip and the heat sink being positioned in the opening.
16. The method of claim 10 , comprising coupling a first semiconductor chip to the first side of the second circuit board over and in thermal contact with the thermally conductive vias, and a second semiconductor chip to the second side of the second circuit board.
17. The method of claim 10 , comprising forming a first plurality of patterned metal lines coupled to first ends of the thermally conductive vias and a second plurality of patterned metal lines coupled to second ends of the thermally conductive vias.
18. The method of claim 10 , comprising forming the thermally conductive vias using instructions stored in a computer readable medium.
19. The method of claim 10 , wherein the thermally conductive vias are electrically non-functional.
20. An apparatus, comprising:
a first circuit board having a plurality of thermally conductive vias;
a second circuit board mounted on the first circuit board over and in thermal contact with the thermally conductive vias, the second circuit board including first side facing the first circuit board and a second and opposite side; and
a first semiconductor chip coupled on the first side of the second circuit board over and in thermal contact with the thermally conductive vias, at least a portion of the first semiconductor chip extending beyond the first side of the second circuit board.
21. The apparatus of claim 20 , comprising an underfill material positioned between and in thermal contact with the second circuit board and at least some of the thermally conductive vias.
22. The apparatus of claim 21 , wherein the underfill material includes thermally conductive particles proximate at least some of the thermally conductive vias.
23. The apparatus of claim 20 , wherein at least a portion of the first semiconductor chip is positioned in the opening.
24. The apparatus of claim 20 , wherein the first circuit board includes an opening, the thermally conductive vias being arranged around a perimeter of the opening.
25. The apparatus of claim 24 , comprising a heat sink coupled to the first semiconductor chip, at least a portion of one or both of the first semiconductor chip and the heat sink being positioned in the opening.
26. The apparatus of claim 20 , comprising a first semiconductor chip coupled to the first side of the second circuit board over and in thermal contact with the thermally conductive vias, and a second semiconductor chip coupled to the second side of the second circuit board.
27. The apparatus of claim 20 , comprising a first plurality of patterned metal lines coupled to first ends of the thermally conductive vias and a second plurality of patterned metal lines coupled to second ends of the thermally conductive vias.
28. The apparatus of claim 20 , wherein the thermally conductive vias are electrically non-functional.