Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.
1. A semiconductor device comprising:
a semiconductor substrate;
a lower conductive pattern disposed on the semiconductor substrate;
an interlayer insulating layer disposed on the semiconductor substrate, the interlayer insulating layer including an upper penetrating hole partially exposing a top surface of the lower conductive pattern;
an upper conductive pattern disposed within the upper penetrating hole and disposed on the top surface of the lower conductive pattern, the upper conductive pattern electrically connected to the lower conductive pattern;
a side spacer disposed within the upper penetrating hole, the side spacer covering an upper side surface of the upper conductive pattern; and
an air gap disposed within the upper penetrating hole,
wherein a boundary of the air gap is bounded by a sidewall of the upper penetrating hole, the side spacer, part of the top surface of the lower conductive pattern, and a lower side surface of the upper conductive pattern, and
wherein the side spacer is spaced apart from the lower conductive pattern by the air gap.
2. The device of claim 1 , wherein the lower side surface of the upper conductive pattern is not covered by the side spacer.
3. The device of claim 1 , wherein a highest level of the air gap is substantially the same as a level of a top surface of the upper conductive pattern.
4. The device of claim 1 , wherein each of the side spacer includes a first side surface being in contact with the upper side of the upper conductive pattern, and a second side surface facing the sidewall of the upper penetrating hole, wherein the second side surface of each of the side spacer is extended in parallel to the sidewall of the upper penetrating hole.
5. The device of claim 1 , wherein the top surface of the lower conductive pattern includes a first recess region, wherein the first recess region corresponds to the part of the lower conductive pattern bounding the air gap.
6. The device of claim 5 , wherein a lowest level of the air gap is substantially the same as a level of a bottom surface of the first recess region.
7. The device of claim 5 , wherein the top surface of the lower conductive pattern further includes a second recess region located at a center region of the top surface of the lower conductive pattern, wherein a level of a bottom surface of the second recess region is lower than a level of a bottom surface of the first recess region.
8. The device of claim 7 , wherein a bottom portion of the upper conductive pattern covers sidewalls and a bottom of the second recess region.
9. The device of claim 7 , wherein a level of a bottom surface of the upper conductive pattern is substantially the same as a level of the bottom surface of the second recess region.
10. The device of claim 9 , wherein a horizontal length of the bottom surface of the upper conductive pattern is substantially equal to a horizontal length of the bottom surface of the second recess region.
11. A semiconductor device comprising:
a semiconductor substrate;
a lower conductive pattern disposed on the semiconductor substrate;
an interlayer insulating layer disposed on the semiconductor substrate, the interlayer insulating layer including an upper penetrating hole partially exposing a top surface of the lower conductive pattern;
an upper conductive pattern disposed within the upper penetrating hole and disposed on the top surface of the lower conductive pattern, the upper conductive pattern electrically connected to the lower conductive pattern;
a side spacer disposed within the upper penetrating hole, the side spacer covering an upper side surface of the upper conductive pattern; and
an air gap disposed within the upper penetrating hole,
wherein the air gap is bounded by a sidewall of the upper penetrating hole, the side spacer, part of the top surface of the lower conductive pattern, and a lower side surface of the upper conductive pattern,
wherein a horizontal length of the air gap between a sidewall of the upper penetrating hole and a side surface of the side spacer is substantially equal to a vertical length of the air gap between the top surface of the lower conductive pattern and a bottom surface of the side spacer.
12. The device of claim 11 , wherein the lower side surface of the upper conductive pattern is not covered by the side spacer.
13. The device of claim 11 , wherein a highest level of the air gap is substantially the same as a level of a top surface of the upper conductive pattern.
14. The device of claim 11 , wherein the horizontal length of the air gap is greater than a horizontal width of the side spacer.
15. The device of claim 11 , wherein the top surface of the lower conductive pattern includes a first recess region, wherein the first recess region corresponds to the part of the lower conductive pattern bounding the air gap.
16. The device of claim 15 , wherein a lowest level of the air gap is substantially the same as a level of a bottom surface of the first recess region.
17. The device of claim 15 , wherein the top surface of the lower conductive pattern further includes a second recess region located at a center region of the top surface of the lower conductive pattern, wherein a level of a bottom surface of the second recess region is lower than a level of a bottom surface of the first recess region.
18. The device of claim 17 , wherein a bottom portion of the upper conductive pattern covers sidewalls and a bottom of the second recess region.
19. The device of claim 17 , wherein a level of a bottom surface of the upper conductive pattern is substantially the same as a level of the bottom surface of the second recess region.
20. The device of claim 19 , wherein a horizontal length of the bottom surface of the upper conductive pattern is substantially equal to a horizontal length of the bottom surface of the second recess region.