IP Library › Granted Patent US 9,219,036
Granted Patent B2
US 9,219,036 · App. 14/679,833 · Granted Dec 22, 2015

Interconnect structure for semiconductor devices

Inventors: Hui-Lin Chang (Hsin-Chu, TW); Hung Chun Tsai (Hsin-Chu, TW); Yung-Cheng Lu (Taipei, TW); Syun-Ming Jang (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/53238H01L21/28556H01L21/32053H01L21/76802H01L21/76834H01L21/76843H01L21/76849H01L21/76867H01L21/76871H01L21/76877H01L21/76883H01L21/76886H01L21/76889H01L23/528H01L23/53233
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,219,036
App. No.
14/679,833
Granted
Dec 22, 2015
Kind
B2
Abstract

A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.

Claims (34)

1. A semiconductor device comprising:

a first dielectric layer;

a trench in the first dielectric layer;

a conductive material at least partially filling the trench, the conductive material comprising copper; and

a cap layer on the conductive material, the cap layer comprising copper-metal silicide, wherein a metal of the copper-metal silicide comprises germanium.

2. The semiconductor device of claim 1 , further comprising a second dielectric layer formed in physical contact over the cap layer and the first dielectric layer.

3. The semiconductor device of claim 1 , further comprising an etch stop layer formed over the cap layer and the first dielectric layer, and a second dielectric layer formed over the etch stop layer.

4. The semiconductor device of claim 1 , wherein the first dielectric layer comprises a low-K dielectric.

5. The semiconductor device of claim 1 , further comprising a barrier layer interposed between the conductive material and sidewalls of the trench.

6. The semiconductor device of claim 5 , wherein the barrier layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

7. The semiconductor device of claim 5 , wherein the barrier layer is conductive.

8. A semiconductor device comprising:

a copper interconnect in a first dielectric layer; and

a copper-metal silicide layer on the copper interconnect, wherein the copper-metal silicide layer comprises arsenic.

9. The semiconductor device of claim 8 , further comprising a second dielectric layer formed directly over the copper-metal silicide layer and the first dielectric layer.

10. The semiconductor device of claim 8 , further comprising an etch stop layer formed over the copper-metal silicide layer and the first dielectric layer, and a second dielectric layer formed over the etch stop layer.

11. The semiconductor device of claim 8 , wherein the first dielectric layer comprises a low-K dielectric.

12. The semiconductor device of claim 8 , further comprising a barrier layer interposed between a conductive material of the copper interconnect and sidewalls of a trench.

13. The semiconductor device of claim 12 , wherein the barrier layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

14. A semiconductor device comprising:

a first dielectric layer;

a copper interconnect formed in the first dielectric layer;

a copper alloy silicide layer on the copper interconnect; and

a second dielectric layer over the first dielectric layer and the copper alloy silicide layer, wherein the copper alloy silicide layer comprises tungsten.

15. The semiconductor device of claim 14 , further comprising an etch stop layer formed between the copper alloy silicide layer and the second dielectric layer.

16. The semiconductor device of claim 14 , wherein the first dielectric layer comprises a low-K dielectric.

17. The semiconductor device of claim 14 , further comprising a conductive barrier layer interposed between copper of the copper interconnect and sidewalls of a trench.

18. A semiconductor device comprising:

a first dielectric layer;

a trench in the first dielectric layer;

a conductive material at least partially filling the trench, the conductive material comprising copper; and

a cap layer on the conductive material, the cap layer comprising copper-metal silicide, wherein a metal of the copper-metal silicide comprises gallium.

19. The semiconductor device of claim 18 , further comprising a conductive barrier layer interposed between the conductive material and the first dielectric layer.

20. The semiconductor device of claim 19 , wherein the conductive barrier layer comprises titanium, titanium nitride, tantalum, or tantalum nitride.

Continuity (8)
Continuation 14336330 · Jul 21, 2014
Division 13710168 · Dec 10, 2012
Continuation 13290811 · Nov 7, 2011
Continuation 12902877 · Oct 12, 2010
Continuation 12638022 · Dec 15, 2009
Continuation 11738982 · Apr 23, 2007
Provisional Application 60919650 · Mar 23, 2007
Related Publication 20150214159A1 · Jul 30, 2015