Integrated circuits with metal-titanium oxide contacts and fabrication methods

1. A method comprising:

obtaining an intermediate semiconductor device, comprising:

a substrate; and

at least one field-effect transistor disposed on the substrate; and

forming at least one contact on the intermediate semiconductor device, comprising:

etching at least one opening in the intermediate semiconductor device;

depositing a chemical oxide into the at least one opening;

applying at least one barrier layer over the intermediate semiconductor device;

depositing at least one dielectric layer over the barrier layer; and

annealing the intermediate semiconductor device.

2. The method of claim 1 , wherein forming at least one contact on the intermediate semiconductor device, further comprises:

forming at least one first contact; and

forming at least one second contact.

3. The method of claim 2 , wherein forming the at least one first contact, comprises:

applying a photo resist layer over a first portion of the intermediate semiconductor device;

etching the at least one dielectric layer from a second portion of the intermediate semiconductor device;

removing the photo resist layer; and

depositing a first metal over the intermediate semiconductor device; and

wherein forming the at least one second contact, comprises:

applying an organic planar layer over the second portion of the intermediate semiconductor device;

etching the first metal and the at least one dielectric layer from the first portion of the intermediate semiconductor device;

removing the organic planar layer; and

depositing a second metal over the intermediate semiconductor device.

4. The method of claim 3 , wherein forming the at least one contact on the intermediate semiconductor device, further comprises:

depositing an adhesion layer over the intermediate semiconductor device;

depositing a third metal layer over the intermediate semiconductor device; and

planarizing the intermediate semiconductor device to expose the at least one first contact and the at least one second contact.

5. The method of claim 4 , wherein the at least one first contact is a pFET contact and the at least one second contact is an nFET contact.

6. The method of claim 1 , wherein forming at least one contact on the intermediate semiconductor device, further comprises:

depositing a stop layer material over the intermediate semiconductor device prior to etching the at least one opening in the intermediate semiconductor device;

forming at least one first contact in the at least one opening in a first portion of the intermediate semiconductor device; and

forming at least one second contact.

7. The method of claim 6 , wherein forming at least one first contact comprises:

etching the at least one dielectric layer from the first portion;

depositing a first metal layer over the intermediate semiconductor device;

depositing an adhesion layer over the first metal layer;

depositing a second metal layer over the adhesion layer; and

planarizing the intermediate semiconductor device to expose at least one first contact.

8. The method of claim 7 , wherein planarizing the intermediate semiconductor device to expose the at least one first contact, comprises:

removing a portion of the second metal layer, a portion of the adhesion layer, a portion of the first metal layer, a portion of the barrier layer, and a portion of the stop layer material.

9. The method of claim 7 , wherein forming at least one second contact comprises:

depositing additional stop layer material over the intermediate semiconductor device;

etching at least one second opening in a second portion of the intermediate semiconductor device;

depositing a chemical oxide into the at least one second opening;

applying at least one barrier layer over the intermediate semiconductor device;

depositing at least one dielectric layer over the barrier layer; and

annealing the intermediate semiconductor device;

etching the at least one dielectric layer from the second portion of the intermediate semiconductor device;

depositing a third metal layer over the intermediate semiconductor device;

depositing an adhesion layer over the third metal layer;

depositing a fourth metal layer over the adhesion layer; and

planarizing the intermediate semiconductor device to expose the at least one first contact and the at least one second contact.

10. The method of claim 9 , wherein planarizing the intermediate semiconductor device to expose the at least one first contact and the at least one second contact, comprises:

removing a portion of the fourth metal layer, a portion of the adhesion layer, a portion of the third metal layer, a portion of the barrier layer, and the stop layer material.

11. The method of claim 9 , wherein the at least one first contact is a p-metal contact and the at least one second contact is an n-metal contact.

12. The method of claim 9 , wherein the at least one first contact is an n-metal contact and the at least one second contact is a p-metal contact.

13. The method of claim 1 , wherein the at least one dielectric layer comprises:

a first dielectric layer; and

a second dielectric layer.

14. The method of claim 13 , wherein annealing the intermediate semiconductor device comprises:

driving oxygen molecules from the second dielectric layer through the first dielectric layer and the at least one barrier layer into the chemical oxide.

15. The method of claim 14 , wherein the second dielectric layer is silicon dioxide, the first dielectric layer is aluminum oxide, the at least one barrier layer is titanium nitride, and the intermediate semiconductor device is annealed at a temperature ranging from approximately 400° C. to 600° C. to drive the oxygen molecules from the silicon dioxide of the second dielectric layer into the chemical oxide to form a titanium dioxide.