Methods of removing gate cap layers in CMOS applications

1. A method, comprising:

forming a sacrificial sidewall spacer adjacent to a gate structure of each of a P-type transistor and an N-type transistor, wherein a material of said sacrificial sidewall spacer has an etch selectivity relative to a material of a gate cap layer formed above said gate structure of each of said P-type and N-type transistors;

forming a masking layer that covers said P-type transistor and exposes at least said gate cap layer of said N-type transistor;

performing a first etching process through said masking layer to selectively remove a portion of said gate cap of said N-type transistor relative to said sacrificial sidewall spacer of said N-type transistor so as to thereby define a reduced thickness gate cap layer for said N-type transistor;

removing said masking layer;

performing a common second etching process on said P-type transistor and said N type transistor to selectively remove said gate cap layer of said P-type transistor and the reduced thickness gate cap layer of said N-type transistor relative to said sacrificial sidewall spacer of said respective P-type and N-type transistors.

2. The method of claim 1 , wherein said P-type transistor is a PFET transistor and said N-type transistor is an NFET transistor.

3. The method of claim 1 , wherein, after performing said first etching process, said reduced thickness gate cap layer of said N-type transistor has a thickness that is approximately equal to a thickness of said gate cap layer of said P-type transistor.

4. The method of claim 1 , wherein said material of said gate cap layer of each of said N-type transistor and said P-type transistor is comprised of silicon nitride.

5. The method of claim 1 , wherein said masking layer is a patterned photoresist masking layer or a patterned hard mask layer.

6. A method, comprising:

forming a P-type transistor and an N-type transistor, wherein each of said transistors comprises a gate structure and a gate cap layer formed above said gate structure, said gate cap layer of said P-type transistor having a thickness that is less than a thickness of said gate cap layer of said N type transistor;

forming a sacrificial sidewall spacer adjacent to said gate structure and said gate cap layer of said P-type transistor and adjacent to said gate structure and said gate cap layer of said N-type transistor, wherein a material of said sacrificial sidewall spacer has an etch selectivity relative to a material of said gate cap layer of each of said P-type and N-type transistors;

forming a masking layer that covers said P-type transistor and exposes at least said gate cap layer of said N-type transistor;

performing a first etching process through said masking layer to selectively remove a portion of said gate cap layer of said N-type transistor relative to said sidewall sacrificial spacer of said N-type transistor so as to thereby define a reduced thickness gate cap layer for said N-type transistor;

removing said masking layer; and

performing a common second etching process on said P-type transistor and said N type transistor to selectively remove the gate cap layer of said P-type transistor and the reduced thickness gate cap layer of said N-type transistor relative to said sacrificial sidewall spacer of said respective P-type and N-type transistors.

7. The method of claim 6 , wherein said gate structure of each of said N-type transistor and said P-type transistor comprise a gate electrode comprised of polysilicon or amorphous silicon.

8. A method, comprising:

forming a PFET transistor and an NFET transistor, wherein each of said transistors comprises a gate structure and a gate cap layer formed above said gate structure, each respective gate cap layer having approximately the same initial thickness;

forming a first masking layer that covers said NFET transistor while exposing said PFET transistor;

with said first masking layer in place, performing at least one first etching process operation on said PFET transistor that reduces a thickness of said gate cap layer of said PFET transistor and thereby defines a reduced thickness gate cap layer for said PFET transistor;

removing said first masking layer;

after removing said first masking layer, forming a sacrificial sidewall spacer adjacent to said gate structure and said reduced thickness gate cap layer of said PFET transistor and adjacent to said gate structure and said gate cap layer of said NFET transistor, wherein a material of said sacrificial sidewall spacer has an etch selectivity relative to a material of said reduced thickness gate cap layer of said PFET transistor and to said gate cap layer of said NFET transistor;

after forming said sacrificial sidewall spacers, forming a second masking layer that covers said PFET transistor and exposes at least said gate cap layer of said NFET transistor;

performing a second etching process through said second masking layer to selectively remove a portion of said gate cap layer of said NFET transistor relative to said sacrificial sidewall spacer of said NFET transistor so as to thereby define a reduced thickness gate cap layer for said NFET transistor;

removing said second masking layer; and

performing a common third etching process on said PFET transistor and said NFET transistor to selectively remove the reduced thickness gate cap layer of said PFET transistor and the reduced thickness gate cap layer of said NFET transistor relative to said sacrificial sidewall spacer of said respective PFET and NFET transistors.

9. The method of claim 8 , wherein, after performing said second etching process, said reduced thickness gate cap layer of said NFET transistor has a thickness that is approximately equal to a thickness said reduced thickness gate cap layer of said NFET transistor.

10. The method of claim 8 , wherein said gate structure of each of said NFET and PFET transistors comprise a gate electrode comprised of polysilicon or amorphous silicon.

11. The method of claim 1 , wherein each of said N-type and P-type transistors comprise a first sidewall spacer positioned adjacent to said gate structure, and wherein said sacrificial spacers are formed to cover said respective first sidewall spacers of said respective N-type and P-type transistors.

12. The method of claim 11 , wherein said material of said sacrificial sidewall spacers has an etch selectivity relative to a material of said first sidewall spacers of said respective N-type and P-type transistors.

13. The method of claim 4 , wherein said material of said sacrificial sidewall spacer of each of said N-type transistor and said P-type transistor is comprised of silicon dioxide.

14. The method of claim 6 , wherein each of said N-type and P-type transistors comprise a first sidewall spacer positioned adjacent to said gate structure, and wherein said sacrificial spacers are formed to cover said respective first sidewall spacers of said respective N-type and P-type transistors.

15. The method of claim 14 , wherein said material of said sacrificial sidewall spacers has an etch selectivity relative to a material of said first sidewall spacers of said respective N-type and P-type transistors.

16. The method of claim 6 , wherein said P-type transistor is a PFET transistor and said N-type transistor is an NFET transistor.

17. The method of claim 6 , wherein, after performing said first etching process, said reduced thickness gate cap layer of said N-type transistor has a thickness that is approximately equal to said thickness of said gate cap layer of said P-type transistor.

18. The method of claim 1 , wherein said gate structure of each of said N-type transistor and said P-type transistor comprise a gate electrode comprised of polysilicon or amorphous silicon.

19. The method of claim 8 , wherein each of said NFET and PFET transistors comprise a first sidewall spacer positioned adjacent to said gate structure, and wherein said sacrificial spacers are formed to cover said first sidewall spacer of said respective NFET and PFET transistors.

20. The method of claim 19 , wherein said material of said sacrificial sidewall spacers has an etch selectivity relative to a material of said first sidewall spacers of said respective NFET and PFET transistors.