Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices

1. A memory cell comprising:

a vertical transistor comprising a surface conduction region;

a ring shaped heater coupled to the surface conductive region through a multiple layer contact, the multiple layer contact comprising a via formed vertically in a dielectric layer, the via filled by a plurality of materials to form the multiple layer contact; and

a phase change memory element comprising a chalcogenic layer formed directly in contact with an entire top surface area of the ring-shaped heater with no intervening layers.

2. The memory cell of claim 1 , wherein a dielectric material fills an interior of the ring-shaped heater.

3. The memory cell of claim 2 , wherein the surface conductive region is of the first conductivity type and is in a body of the vertical transistor and arranged on top of a channel region and a buried conductive region of the vertical transistor.

4. The memory cell of claim 3 , wherein the buried conductive region is a source region of the vertical transistor and the surface conductive region is a drain region of the vertical transistor.

5. The memory cell of claim 3 , wherein a gate insulation region of the vertical transistor completely laterally surrounds a channel region and a gate region completely laterally surrounds a gate insulation region.

6. The memory cell of claim 5 , wherein the gate insulation region and the gate region extend on two sides of the channel region.

7. The memory cell of claim 5 , wherein the buried conductive region, the channel region and at least part of the surface conductive region comprise monocrystalline material and at least part of the gate region comprises polycrystalline material.

8. The memory cell of claim 1 , wherein the surface conductive region comprises a first semiconductor material region and a first metal silicide region arranged on top of the first semiconductor material region.

9. A memory cell comprising:

a phase change memory element coupled to a surface conductive region of a vertical transistor,

wherein the phase change memory element comprises a chalcogenic layer; and

a ring-shaped heater coupled to the surface conductive region through a multiple layer contact,

the multiple layer contact comprising a via formed vertically in a dielectric layer of the vertical transistor,

the via filled by a plurality of materials to form the multiple layer contact,

wherein the chalcogenic layer is directly in contact with an entire top surface area of the ring-shaped heater with no intervening layers.

10. The memory cell of claim 9 , wherein the plurality of materials comprise Ti or TiN.

11. The memory cell of claim 10 , wherein the Ti or TiN material comprises a double layer of Ti/TiN and tungsten.

12. The memory cell of claim 9 , wherein the via extends as far as a silicide region overlying source/drain regions of the vertical transistor.

13. The memory cell of claim 12 , wherein a second silicide region overlies a gate region of the vertical transistor.

14. The memory cell of claim 13 , wherein the gate region comprises a semiconductor material region and a metal silicide region, the metal silicide region being arranged on top of the semiconductor material region.

15. The memory cell of claim 9 , wherein the ring shaped heater is provided with a second via and the walls of the second via are coated with a spacing layer.

16. The memory cell of claim 15 , wherein the spacing layer comprises silicon nitride.

17. The memory cell of claim 16 , wherein the second via further comprises a resistive layer.

18. The memory cell of claim 17 , wherein the resistive layer comprises at least one of TiSiN, TiAlN, or TiSiC.

19. The memory cell of claim 18 ,

wherein the second via further comprises a filling material.

20. The memory cell of claim 19 , wherein the filling material comprises silicon oxide.