High speed, high density, low power die interconnect system
A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.
1. A system for interconnection of a plurality of dies, the system comprising:
a first die including a first wafer portion, wherein the first wafer portion comprises:
a first die substrate;
a first die side edge;
a first die conducting layer;
a plurality of interposed first die dielectric layers between the first die conducting layer and a top surface of the first die;
a plurality of interposed first die conducting layers between the first die conducting layer and the top surface of the first die, wherein the plurality of interposed first die conducting layers are separated from each other by ones of the plurality of first die dielectric layers; and
a first die contact disposed on the first die side edge and electrically connected to the first die conducting layer, wherein the electrical connection between the first die conducting layer and the first die contact does not traverse all of the plurality of interposed first die dielectric layers and all of the plurality of interposed first die conducting layers;
a second die including a second wafer portion, wherein the second wafer portion comprises:
a second die substrate;
a second die side edge;
a second die conducting layer;
a plurality of interposed second die dielectric layers between the second die conducting layer and a top surface of the second die;
a plurality of interposed second die conducting layers between the second die conducting layer and the top surface of the second die, wherein the plurality of interposed second die conducting layers are separated from each other by ones of the plurality of second die dielectric layers; and
a second die contact disposed on the second die side edge and electrically connected to the second die conducting layer, wherein the electrical connection between the second die conducting layer and the second die contact does not traverse all of the plurality of interposed second die dielectric layers and all of the plurality of interposed second die conducting layers;
wherein the second die is positioned horizontally relative to the first die such that the first die side edge opposes the second die side edge; and
an interconnect structure disposed at least partially between the first die side edge and the second die side edge, wherein the interconnect structure couples the first die contact with the second die contact.
2. The system of claim 1 , wherein the interconnect structure provides direct coupling and comprises at least one of a rod, a ball, a dual balls, a bar, a cylinder, a bump, a slug, a carbon nanotube, a conductive contact pad, an enlarged contact, a tapered rod, or a fiber optic cable.
3. The system of claim 1 , wherein:
at least one of the first die or the second die comprises features to facilitate mating with the interconnect structure; and
the features comprise at least one of dogleg cuts, grooves, notches, conductive contact pads, enlarged contacts, tapered side edges, terraces, bumps, tapered rods, or stepped vias.
4. The system of claim 1 , further comprising a bus coupled to at least one of the first die conducting layers or at least one of the second die conducting layers, wherein the bus is coupled to the interconnect structure.
5. The system of claim 1 , wherein at least one of the first die or the second die further comprise at least one of active elements or passive elements.
6. The system of claim 1 , wherein the interconnect structure provides indirect coupling, and wherein the indirect coupling comprises at least one of inductive coupling, capacitive coupling, or wireless coupling.
7. A system for interconnection of a plurality of dies, the system comprising:
a first die including a first wafer portion, wherein the first wafer portion comprises:
a first die substrate;
a first die side edge;
a first die conducting layer;
a plurality of interposed first die dielectric layers between the first die conducting layer and a top surface of the first die;
a plurality of interposed first die conducting layers between the first die conducting layer and the top surface of the first die, wherein the plurality of interposed first die conducting layers are separated from each other by ones of the plurality of first die dielectric layers; and
a first die contact disposed on the first die side edge and electrically connected to the first die conducting layer, wherein the electrical connection between the first die conducting layer and the first die contact does not traverse all of the plurality of interposed first die dielectric layers and all of the plurality of interposed first die conducting layers;
a second die including a second wafer portion, wherein the second wafer portion comprises:
a second die substrate;
a second die side edge;
a second die conducting layer;
a plurality of interposed second die dielectric layers between the second die conducting layer and a top surface of the second die;
a plurality of interposed second die conducting layers between the second die conducting layer and the top surface of the second die, wherein the plurality of interposed second die conducting layers are separated from each other by ones of the plurality of second die dielectric layers; and
a second die contact disposed on the second die side edge and electrically connected to the second die conducting layer, wherein the electrical connection between the second die conducting layer and the second die contact does not traverse all of the plurality of interposed second die dielectric layers and all of the plurality of interposed second die conducting layers;
wherein the second die is positioned horizontally relative to the first die such that the first die side edge opposes the second die side edge; and
at least one interconnect structure at least partially disposed between the first die contact and the second die contact such that the at least one interconnect structure couples the first die contact and the second die contact.
8. The system of claim 7 , wherein the interconnect structure provides direct coupling and comprises at least one of a rod, a ball, a dual balls, a bar, a cylinder, a bump, a slug, a carbon nanotube, a conductive contact pad, an enlarged contact, a tapered rod, or a fiber optic cable.
9. The system of claim 7 , wherein:
at least one of the first die or the second die comprises features to facilitate mating with the interconnect structure; and
the features comprise at least one of dogleg cuts, grooves, notches, conductive contact pads, enlarged contacts, tapered side edges, terraces, bumps, tapered rods, or stepped vias.
10. The system of claim 7 , further comprising a bus coupled to at least one of the first die conducting layers or at least one of the second die conducting layers, wherein the bus is coupled to the interconnect structure.
11. The system of claim 7 , wherein at least one of the first die or the second die further comprise at least one of active elements or passive elements.
12. The system of claim 7 , wherein the interconnect structure provides indirect coupling, and wherein the indirect coupling comprises at least one of inductive coupling, capacitive coupling, or wireless coupling.