III-N device structures having a non-insulating substrate
Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer.
1. A III-N device, comprising:
a silicon substrate having a first side and a second side opposite the first side;
a nucleation layer on the first side of the silicon substrate;
a stress management layer on the nucleation layer;
a first III-N material layer on the stress management layer, the first III-N material layer including a channel layer having a conductive channel therein;
a second III-N material layer on the first III-N material layer;
an electrode contacting the channel;
a barrier layer disposed on the second side of the silicon substrate, the barrier layer being less electrically conductive than the silicon substrate; and
an electrically conductive layer on a side of the barrier layer opposite the silicon substrate; wherein
the electrode is directly connected to the electrically conductive layer.
2. The device of claim 1 , wherein, the electrically conductive layer is a portion of a device package.
3. The device of claim 1 , wherein the electrically conductive layer is configured to be grounded or connected to a ground.
4. The device of claim 1 , wherein the barrier layer is configured to reduce, relative to a device lacking the barrier layer, a leakage current from the channel layer to the electrically conductive layer during device operation.
5. The device of claim 1 , wherein the silicon substrate is a conductive or partially conductive substrate.
6. The device of claim 1 , wherein the barrier layer includes high electrical resistivity material.
7. The device of claim 1 , wherein the barrier layer includes electrically insulating material.
8. The device of claim 1 , wherein the barrier layer includes thermally conductive material.
9. The device of claim 1 , wherein the barrier layer includes AIN or a ceramic material.
10. The device of claim 9 , wherein the conductive channel is a 2DEG channel, and wherein a compositional difference between the first III-N material layer and the second III-N material layer induces the 2DEG channel in the first III-N material layer.
11. The device of claim 10 , wherein the electrode is a source contact, the device further comprising a drain contact and a gate, the source and drain contacts and gate being over a side of the second III-N material layer opposite the first III-N material layer.
12. A III-N device, comprising:
a silicon substrate having a first side and a second side opposite the first side;
a first III-N material layer on the first side of the silicon substrate, the first III-N material layer including a channel layer having a conductive channel therein;
a second III-N material layer on the first III-N material layer;
an electrode contacting the channel;
a barrier layer disposed on the second side of the silicon substrate, the barrier layer being less electrically conductive than the silicon substrate; and
an electrically conductive layer on a side of the barrier layer opposite the silicon substrate;
wherein the barrier layer is bonded to the silicon substrate, and the electrode is directly connected to the electrically conductive layer.
13. The device of claim 12 , wherein, the electrically conductive layer is a portion of a device package.
14. The device of claim 12 , wherein the electrically conductive layer is configured to be grounded or connected to a ground.
15. The device of claim 12 , wherein the barrier layer is configured to reduce, relative to a device lacking the barrier layer, a leakage current from the channel layer to the electrically conductive layer during device operation.
16. The device of claim 12 , wherein the silicon substrate is a conductive or partially conductive substrate.
17. The device of claim 12 , wherein the barrier layer includes high electrical resistivity material.
18. The device of claim 12 , wherein the barrier layer includes electrically insulating material.
19. The device of claim 12 , wherein the barrier layer includes thermally conductive material.
20. The device of claim 12 , wherein the barrier layer includes AlN or a ceramic material.
21. The device of claim 12 , wherein the conductive channel is a 2DEG channel, and wherein a compositional difference between the first III-N material layer and the second III-N material layer induces the 2DEG channel in the first III-N material layer.
22. The device of claim 21 , wherein the electrode is a source contact, the device further comprising a drain contact and a gate, the source and drain contacts and gate being over a side of the second III-N material layer opposite the first III-N material layer.
23. A III-N device, comprising:
a silicon substrate having a first side and a second side opposite the first side;
a first III-N material layer on the first side of the silicon substrate, the first III-N material layer including a channel layer;
a second III-N material layer on the first III-N material layer;
a barrier layer disposed on the second side of the silicon substrate, the barrier layer being less electrically conductive than the silicon substrate;
an electrically conductive layer on a side of the barrier layer opposite the silicon substrate; and
a source contact, a drain contact and a gate; wherein
a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer, the gate is adjacent to the second III-N material layer, the source contact and drain contact are in electrical contact with the 2DEG, and the device is an enhancement mode FET; and
the source contact is directly connected to the electrically conductive layer.
24. The device of claim 23 , wherein, the electrically conductive layer is a portion of a device package.
25. The device of claim 23 , wherein the electrically conductive layer is configured to be grounded or connected to a ground.
26. The device of claim 23 , wherein the barrier layer is configured to reduce, relative to a device lacking the barrier layer, a leakage current from the channel layer to the electrically conductive layer during device operation.
27. The device of claim 23 , wherein the silicon substrate is a conductive or partially conductive substrate.
28. The device of claim 23 , wherein the barrier layer includes AIN or a ceramic material.
29. A III-N device, comprising:
a silicon substrate having a first side and a second side opposite the first side;
a first III-N material layer on the first side of the silicon substrate, the first III-N material layer including a channel layer;
a second III-N material layer on the first III-N material layer; and
a barrier layer disposed on the second side of the silicon substrate, the barrier layer being less electrically conductive than the silicon substrate;
an electrically conductive layer on a side of the barrier layer opposite the silicon substrate; and
a source contact, a drain contact and a gate; wherein
a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer, the gate is in contact with the second III-N material layer, the source contact and drain contact are in electrical contact with the 2DEG, and the device is a depletion mode FET; and
the source contact is directly connected to the electrically conductive layer.
30. A III-N device, comprising:
a silicon substrate having a first side and a second side opposite the first side;
a first III-N material layer on the first side of the silicon substrate, the first III-N material layer including a channel layer;
a second III-N material layer on the first III-N material layer;
a barrier layer disposed on the second side of the silicon substrate, the barrier layer being less electrically conductive than the silicon substrate;
an electrically conductive layer on a side of the barrier layer opposite the silicon substrate;
an anode contacting at least one of the first and second III-N material layers; and
a cathode; wherein
a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer, the cathode contacts the 2DEG channel, and the device is a diode; and
the anode is directly connected to the electrically conductive layer.