Methods of forming semiconductor devices using hard mask layers
A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures.
1. A method of forming a semiconductor structure comprising:
forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction;
forming a trench through the hard mask layer into the silicon fin using the photolithography mask, the trench extending in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction; and then
widening a portion of the trench formed by the hard mask layer relative to a lower portion of the trench defined by the first and second fin structures.
2. The method of claim 1 wherein forming a photolithography mask is preceded by:
forming the silicon fin;
forming a lower field insulating layer adjacent to the silicon fin; and
forming the hard mask layer on the silicon fin and on the lower field insulating layer.
3. The method of claim 2 wherein the lower field insulating layer and the hard mask layer comprise respective materials having an etch selectivity relative to one another.
4. The method of claim 2 wherein:
forming a trench through the hard mask layer comprises etching through the hard mask layer to expose ends of the first and second fin structures separated by the trench; and
widening a portion of the trench comprises widening the portion of the trench above the exposed ends to expose end corners of the first and second fin structures.
5. The method of claim 4 wherein widening a portion of the trench comprises isotropic etching of the hard mask layer in the trench.
6. The method of claim 5 wherein isotropic etching of the hard mask layer in the trench comprises recessing side walls of the hard mask layer equal amounts in opposing directions to widen the portion of the trench.
7. The method of claim 4 further comprising:
depositing an upper field insulating material into the trench through the hard mask layer to cover and conform to the end corners of the first and second fin structures.
8. The method of claim 7 further comprising:
removing the hard mask layer from the first and second fin structures to expose an upper surface of the lower field insulating layer;
etching upper surfaces of the lower field insulating layer and of the upper field insulating material to reduce respective thicknesses thereof so that the upper field insulating material remains conforming to the end corners of the first and second fin structures; and
forming a conductive layer on the upper surface of the upper field insulating material.
9. The method of claim 8 wherein etching the upper surfaces comprises etching equal amounts of the lower field insulating layer and the upper field insulating material so that the upper surface of the upper field insulating material remains to cover uppermost surfaces of the first and second fin structures.
10. The method of claim 8 wherein etching the upper surfaces comprises etching the lower field insulating layer and the upper field insulating material to reduce respective thicknesses thereof so that the upper surface of the upper field insulating material exposes uppermost surfaces of the first and second fin structures.
11. The method of claim 8 wherein forming a conductive layer comprises forming a gate-last dummy gate.
12. The method of claim 7 further comprising:
forming first and second epitaxial source/drain regions in the first and second fin structures, respectively, wherein uppermost surfaces of the first and second epitaxial source/drain regions are above an uppermost surface of the upper field insulating material.
13. The method of claim 7 further comprising:
forming first and second epitaxial source/drain regions in the first and second fin structures, respectively, wherein uppermost surfaces of the first and second epitaxial source/drain regions are coplanar with an uppermost surface of the upper field insulating material.
14. The method of claim 1 wherein forming a photolithography mask is preceded by:
forming a silicon layer;
forming a hard mask material on the silicon layer; and
etching the hard mask material and the silicon layer to form the silicon fin having the hard mask layer thereon.
15. The method of claim 14 further comprising:
forming a trench through the hard mask layer comprises etching through the hard mask layer to form the trench exposing the hard mask layer therein and to expose ends of the first and second fin structures separated by the trench;
widening a portion of the trench comprises widening the portion of the trench provided by the exposed hard mask layer in the trench to expose end corners of the first and second fin structures.
16. The method of claim 15 wherein widening a portion of the trench comprises isotropic etching of the hard mask layer in the trench.
17. The method of claim 16 wherein isotropic etching of the hard mask layer in the trench comprises recessing side walls of the hard mask layer equal amounts in opposing directions to widen the portion of the trench.
18. The method of claim 14 further comprising:
depositing a field insulating material in the trench conformal with the end corners of the first and second fin structures.
19. The method of claim 18 further comprising:
removing the hard mask layer from the first and second fin structures to expose an upper surface of the field insulating layer; and
forming a conductive layer on an upper surface of the field insulating material.
20. The method of claim 19 wherein forming a conductive layer comprises forming a gate-last dummy gate.
21. The method of claim 18 further comprising:
forming first and second epitaxial source/drain regions in the first and second fin structures, respectively, wherein uppermost surfaces of the first and second epitaxial source/drain regions are above an uppermost surface of the field insulating material.
22. The method of claim 18 further comprising:
forming first and second epitaxial source/drain regions in the first and second fin structures, respectively, wherein uppermost surfaces of the first and second epitaxial source/drain regions are coplanar with an uppermost surface of the field insulating material.
23. The method of claim 19 further comprising:
forming a lower field insulating layer adjacent to the silicon fin in the first direction.
24. The method of claim 1 wherein forming a photolithography mask on a silicon fin comprises forming the photolithography mask on a finFET silicon fin.
25. A method of forming a semiconductor structure comprising:
forming a field insulating layer including a protruding portion that protrudes from a trench to conform to end corners of first and second separated fins, to form a tuck structure that overlaps the end corners of the first and second separated fin structures;
forming a finFET on the first fin structure; and
forming a conductive layer extending from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second fin structures.
26. The method of claim 25 wherein forming a conductive layer comprises forming a gate-last dummy gate.
27. A semiconductor device comprising:
first and second fin structures directly adjacent to one another and separated by a trench, wherein the first and second fin structures include respective first and second end corners forming an opening of the trench;
a field insulating layer including a protruding portion that protrudes from the trench to conform to the end corners of the first and second fin structures to form a tuck structure that overlaps the first and second fin structures;
a finFET on the first fin structure;
a conductive layer extending from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second fin structures; and
a source/drain region in the first fin structure.
28. The device of claim 27 further comprising:
a conductive layer side wall spacer on the conductive layer including an outermost edge that is recessed from an outermost edge of the tuck structure.
29. The device of claim 27 wherein the source/drain region comprises an epitaxial source/drain region contacting an outermost edge of the tuck structure.