Memory arrays
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
1. A memory array, comprising:
a stack of alternating first and second levels;
channel material pillars extending through the stack;
vertically-stacked memory cell strings along the channel material pillars; and
a common source under the stack and electrically coupled to the channel material pillars; the common source comprising conductive protective material over and directly against metal silicide; the conductive protective material comprising a composition other than metal silicide, and including germanium and silicon.
2. The memory array of claim 1 wherein the channel material pillars are hollow.
3. The memory array of claim 1 wherein the channel material pillars are not hollow.
4. The memory array of claim 1 wherein the metal silicide comprises tungsten silicide.
5. The memory array of claim 1 wherein the germanium is conductively doped.
6. The memory array of claim 1 wherein the silicon is conductively doped.
7. The memory array of claim 1 wherein the channel material pillars comprise silicon, and wherein silicon of the channel material pillars directly contacts the conductive protective material.
8. The memory array of claim 1 wherein the protective material comprises two portions, with one of the portions primarily comprising the germanium and the other of the portions primarily comprising the silicon.