IP Library Granted Patent US 9,293,194
Granted Patent B2
US 9,293,194 · App. 13/471,484 · Granted Mar 22, 2016

Programming and erasure schemes for analog memory cells

Inventors: Eyal Gurgi (Petah-Tikva, IL); Yoav Kasorla (Even Yehuda, IL); Ofir Shalvi (Raanana, IL)
Assignee: Apple Inc.
G11C11/5628G11C16/04G11C16/349
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Quick Facts
Patent No.
US 9,293,194
App. No.
13/471,484
Granted
Mar 22, 2016
Kind
B2
Abstract

A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of the memory cells in accordance with the set parameter.

Claims (32)

1. A method for data storage, comprising:

in a memory that includes multiple memory cells, applying to a group of the memory cells a programming operation that sets the memory cells in the group to respective threshold values dependent upon received data;

completing the programming operation by verifying the memory cells in the group have reached their respective threshold value;

executing a separate verification operation to assess a performance measure of the programming operation applied to the group of the memory cells, wherein executing the separate verification operation includes determining a duration of the programming operation and determining the performance measure dependent upon a comparison of the duration of the programming operation to a predefined range of programming times; and

assessing a health status of a memory block in the memory that includes the group, based on the assessed performance measure of the programming operation.

2. The method according to claim 1 , further comprising determining that the performance measure deviates from the predefined range of programming times in response to a determination that the duration of the programming operation is less than a minimum programming duration.

3. The method according to claim 1 , wherein assessing the health status further comprises marking the memory block as bad when the performance measure deviates from the predefined range of programming times.

4. The method according to claim 1 , wherein assessing the health status comprises marking the memory block as subject to additional evaluation when the performance measure deviates from the predefined range of programming times.

5. The method according to claim 1 , wherein assessing the health status comprises setting a storage configuration for subsequent data storage in the memory block depending on the performance measure.

6. An apparatus for data storage, comprising:

a memory, which includes multiple memory cells; and

storage circuitry, which is configured to:

apply to a group of the memory cells a programming operation that sets the memory cells in the group to respective threshold values dependent upon received data;

complete the programming operation by verifying the memory cells in the group have reached their respective threshold value;

execute a separate verification operation to assess a performance measure of the programming operation applied to the group of the memory cells; and

assess a health status of a memory block in the memory that includes the group, based on the assessed performance measure of the programming operation;

wherein to execute the separate verification operation, the storage circuit is further configured to:

determine a duration of the programming operation; and

determine the performance measure dependent upon a comparison of the duration of the programming operation to a predefined range of programming times.

7. The apparatus according to claim 6 , wherein the storage circuitry is further configured to determine that the performance measure deviates from the predefined range of programming times in response to a determination that the duration of the programming operation is less than a minimum programming duration.

8. The apparatus according to claim 6 , wherein the storage circuitry is further configured to mark the memory block as bad when the performance measure deviates from the predefined range of programming times.

9. The apparatus according to claim 6 , wherein the storage circuitry is further configured to mark the memory block as subject to additional evaluation when the performance measure deviates from the predefined range of programming times.

10. The apparatus according to claim 6 , wherein the storage circuitry is further configured to set a storage configuration for subsequent data storage in the memory block depending on the performance measure.

11. A computer-accessible non-transitory storage medium having program instructions stored therein that, in response to execution by a processor, cause the processor to perform operations comprising:

applying to a group of the memory cells a programming operation that sets the memory cells in the group to respective threshold values dependent upon received data;

completing the programming operation by verifying the memory cells in the group have reached their respective threshold value;

executing a separate verification operation to assess a performance measure of the programming operation applied to the group of the memory cells, wherein executing the separate verification operation includes determining a duration of the programming operation and determining the performance measure dependent upon a comparison of the duration of the programming operation to a predefined range of programming times; and

assessing a health status of a memory block in the memory that comprises the group, based on the assessed performance measure of the programming operation.

12. The computer-accessible non-transitory storage medium of claim 11 , wherein the operations further comprise determining that the performance measure deviates from the predefined range of programming times in response to a determination that the duration of the programming operation is less than a minimum programming duration.

13. The computer-accessible non-transitory storage medium of claim 11 , wherein assessing the health status comprises marking the memory block as bad when the performance measure deviates from the predefined range of programming times.

14. The computer-accessible non-transitory storage medium of claim 11 , wherein assessing the health status comprises marking the memory block as subject to additional evaluation when the performance measure deviates from the predefined range of programming times.

15. The computer-accessible non-transitory storage medium of claim 11 , wherein assessing the health status comprises setting a storage configuration for subsequent data storage in the memory block depending on the performance measure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2012
From: ANOBIT TECHNOLOGIES LTD.
To: APPLE INC.
Reel/Frame 028399/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2012
From: GURGI, EYAL; KASORLA, YOAV; SHALVI, OFIR
To: ANOBIT TECHNOLOGIES LTD
Reel/Frame 028206/0653 →
Continuity (4)
Continuation In Part 13356694 · Jan 24, 2012
Provisional Application 61486341 · May 16, 2011
Provisional Application 61436619 · Jan 27, 2011
Related Publication 20120224423A1 · Sep 6, 2012