Semiconductor package having a cap unit with concave portion and method of manufacturing the same
A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.
1. A semiconductor package comprising:
a semiconductor chip having a signal input terminal and a signal output terminal; and
a cap unit provided above the semiconductor chip, the cap unit including,
a concave portion forming a hollow structure between the semiconductor chip and the cap unit, the concave portion having a first inner side surface and a second inner side surface facing each other, a first line of intersection between the first inner side surface and a plane parallel to a surface of the semiconductor chip and a second line of intersection between the second inner side surface and the plane are not parallel to each other,
a first electrode electrically connected to the signal input terminal, one end of the first electrode exposed at a first surface of the cap unit and the other end of the first electrode exposed at a second surface of the cap unit opposite to the first surface, and
a second electrode electrically connected to the signal output terminal, one end of the second electrode exposed at the first surface of the cap unit and the other end of the second electrode exposed at a third surface of the cap unit opposite to the first surface.
2. The package according to claim 1 , wherein the first inner side surface and the second inner side surface are located in a direction of signal propagation in the semiconductor chip.
3. The package according to claim 1 , wherein the first inner side surface has a first concave-convex pattern, and the second inner side surface has a second concave-convex pattern.
4. The package according to claim 3 , wherein the first concave-convex pattern and the second concave-convex pattern differ from each other.
5. The package according to claim 3 , wherein the first concave-convex pattern and the second concave-convex pattern do not have regularity.
6. The package according to claim 1 , wherein at least part of the cap unit is made of silicon (Si).
7. The package according to claim 1 , wherein at least part of the first and second electrodes is made of copper (Cu).
8. The package according to claim 1 , wherein the semiconductor chip is an MMIC (Monolithic Microwave Integrated Circuit).
9. The package according to claim 1 , further comprising:
an insulating layer formed on the cap unit; and
an interconnect layer formed on the insulating layer, the interconnect layer being electrically connected to one of the signal input terminal and the signal output terminal.