Semiconductor contacts and methods of fabrication
Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.
1. A semiconductor structure comprising:
a semiconductor substrate;
a plurality of semiconductor fins disposed on the semiconductor substrate;
a shallow trench isolation between fins of the plurality of fins;
a first gate disposed on the semiconductor substrate adjacent to at least one fin of the plurality of fins;
a second gate disposed over a non-active area of the substrate;
a first insulator layer disposed between the first gate and the second gate, and in direct physical contact with the non-active area of the substrate;
a metal layer disposed on, and in contact with, the at least one fin of the plurality of fins;
a second insulator layer disposed over the first insulator layer and metal contact layer;
a first contact via disposed in the second insulator layer and making contact with the contact metal layer; and
a second contact via disposed in the second insulator layer and the first insulator layer, and making contact with the second gate.
2. The semiconductor structure of claim 1 , wherein the first insulator layer is comprised of silicon oxycarbide.
3. The semiconductor structure of claim 2 , wherein the second insulator layer is comprised of silicon oxide.
4. The semiconductor structure of claim 3 , further comprising a capping layer disposed over the first gate.
5. The semiconductor structure of claim 4 , wherein the capping layer is comprised of silicon nitride.
6. The semiconductor structure of claim 1 , wherein the first contact and second contact vias are comprised of tungsten.
7. A method of forming a semiconductor structure, comprising:
forming a plurality of fins on a semiconductor substrate;
removing a portion of at least one fin of the plurality of fins;
depositing a shallow trench isolation between fins of the plurality of fins;
forming a plurality of gates on the semiconductor substrate, oriented perpendicular to, and disposed over, the plurality of fins such that a first gate of the plurality of gates is adjacent to the at least one fin, and a second gate of the plurality of gates is distanced from the at least one fin and disposed over the shallow trench isolation;
depositing a capping layer over the substrate, the first gate, and the second gate to form a cap over the first gate and the second gate;
depositing a sacrificial layer on the capping layer;
removing a portion of the sacrificial layer;
removing the capping layer from the second gate and area of substrate disposed between the first gate and the second gate;
depositing a first insulator layer on the capping layer, the substrate, and the second gate;
removing the sacrificial layer to expose the fin;
depositing a metal layer over the fin;
depositing a second insulator layer over the metal layer and the first insulator layer;
forming a first cavity in the second insulator layer and the first insulator layer to expose the second gate;
forming a second cavity in the second insulator layer to expose the metal layer; and
filling the first cavity and second cavity with a conductive material.
8. The method of claim 7 , wherein depositing a capping layer comprises depositing silicon nitride.
9. The method of claim 7 , wherein depositing a sacrificial layer comprises depositing silicon oxide.
10. The method of claim 9 , wherein depositing a first insulator layer comprises depositing silicon oxide.
11. The method of claim 10 , wherein depositing the second insulator layer comprises depositing silicon oxycarbide.
12. The method of claim 10 , wherein removing the sacrificial layer to expose the fin is performed with a hydrofluoric acid wet etch.
13. The method of claim 10 , wherein forming a first cavity in the second insulator layer is performed using a reactive ion etch process.
14. A method of forming a semiconductor structure, comprising:
forming a plurality of fins on a semiconductor substrate;
removing a portion of at least one fin of the plurality of fins;
depositing a shallow trench isolation between fins of the plurality of fins;
forming a plurality of gates on the semiconductor substrate, oriented perpendicular to, and disposed over, the plurality of fins, such that a first gate of the plurality of gates is adjacent to the at least one fin, and a second gate of the plurality of gates is distanced from the at least one fin and disposed over a non-active area portion of the substrate;
depositing a capping layer over the substrate, the first gate, and the second gate;
depositing a sacrificial layer on the capping layer;
removing a portion of the sacrificial layer between the first gate and the second gate;
removing the capping layer from the second gate and an area of the substrate disposed between the first gate and the second gate;
depositing a first insulator layer on the second gate, and the area of the substrate disposed between the first gate the second gate;
removing the sacrificial layer;
removing the capping layer to expose the fin;
depositing a metal layer over the fin;
depositing a second insulator layer over the metal layer and first insulator layer;
depositing a resist layer over the second insulator layer;
simultaneously forming a plurality of cavities in the resist layer using an Extreme Ultraviolet Lithography process;
extending the plurality of cavities through at least one of the second insulator layer and the first insulator layer; and
filling the plurality of cavities with a conductive material.
15. The method of claim 14 , wherein depositing the capping layer comprises depositing silicon nitride.
16. The method of claim 14 , wherein depositing the sacrificial layer comprises depositing silicon oxide.
17. The method of claim 16 , wherein depositing the first insulator layer comprises depositing silicon oxycarbide.
18. The method of claim 16 , wherein removing the sacrificial layer is performed with a hydrofluoric acid wet etch.
19. The method of claim 14 , wherein filling the plurality of cavities with a conductive material comprises filling the plurality of cavities with tungsten.
20. The method of claim 14 , wherein extending the plurality of cavities through the second insulator layer and first insulator layer is performed using a reactive ion etch process.