Testable power-on-reset circuit
An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage.
1. An integrated circuit, comprising:
a voltage divider for receiving a first supply voltage and outputting a second supply voltage;
a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold;
an inverter connected to the POR circuit for receiving the POR voltage signal and generating an inverted POR voltage signal;
a level-shifter connected to the POR circuit and the inverter for receiving the POR voltage signal and the inverted POR voltage signal, respectively, and generating a level-shifted POR voltage signal;
a buffer connected to the level-shifter for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal; and
a flip-flop having a data input terminal for receiving the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the level-shifter for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal.
2. The integrated circuit of claim 1 , further comprising a processor connected to the output terminal of the flip-flop for receiving the voltage-monitor signal and determining a voltage level of the first supply voltage when the second supply voltage equals the POR de-assertion threshold, and wherein the processor further determines the POR de-assertion threshold based on the voltage level of the first supply voltage.
3. The integrated circuit of claim 2 , wherein the level-shifted POR voltage signal is generated at the voltage level of the first supply voltage.
4. The integrated circuit of claim 1 , wherein the voltage divider includes a resistor-ladder circuit having a voltage tap, wherein the second supply voltage is output at the voltage tap.
5. The integrated circuit of claim 4 , wherein the inverter comprises:
a first transistor having a source terminal connected to the voltage tap of the resistor-ladder circuit for receiving the second supply voltage and a gate terminal connected to the POR circuit for receiving the POR voltage signal; and
a second transistor having a source terminal connected to ground, a gate terminal connected to the POR circuit for receiving the POR voltage signal, and a drain terminal connected to a drain terminal of the first transistor for outputting the inverted POR voltage signal.
6. The integrated circuit of claim 1 , wherein the level-shifter comprises:
a first transistor having a source terminal connected to ground and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
a second transistor having a source terminal connected to ground and a gate terminal connected to the inverter for receiving the inverted POR voltage signal;
a third transistor having a source terminal connected to the first supply voltage, a gate terminal connected to a drain terminal of the second transistor, and a drain terminal connected to a drain terminal of the first transistor; and
a fourth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the drain terminal of the second transistor for outputting the level-shifted POR voltage signal.
7. The integrated circuit of claim 1 , wherein the buffer comprises:
a first inverter connected to the level-shifter for receiving the level-shifted POR voltage signal and generating an inverted level-shifted POR voltage signal; and
a second inverter connected to the first inverter for receiving the inverted level-shifted POR voltage signal and generating the delayed level-shifted POR voltage signal.
8. The integrated circuit of claim 7 , wherein the first inverter comprises:
a first transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the level-shifter for receiving the level-shifted POR voltage signal; and
a second transistor having a source terminal connected to ground, a gate terminal connected to the level-shifter for receiving the level-shifted POR voltage signal and a drain terminal connected to a drain terminal of the first transistor for outputting the inverted level-shifted POR voltage signal.
9. The integrated circuit of claim 8 , wherein the second inverter comprises:
a third transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the drain terminal of the first transistor for receiving the inverted level-shifted POR voltage signal; and
a fourth transistor having a source terminal connected to ground, a gate terminal connected to the drain terminal of the first transistor for receiving the inverted level-shifted POR voltage signal, and a drain terminal connected to a drain terminal of the third transistor for outputting the delayed level-shifted POR voltage signal.
10. An integrated circuit, comprising:
a voltage divider for receiving a first supply voltage and outputting a second supply voltage;
a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold;
a first transistor having a source terminal connected to the voltage divider for receiving the second supply voltage and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
a second transistor having a source terminal connected to ground, a gate terminal connected to the POR circuit for receiving the POR voltage signal, and a drain terminal connected to a drain terminal of the first transistor for generating an inverted POR voltage signal;
a third transistor having a source terminal connected to ground and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
a fourth transistor having a source terminal connected to ground and a gate terminal connected to the drain terminal of the second transistor for receiving the inverted POR voltage signal;
a fifth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to a drain terminal of the fourth transistor, and a drain terminal connected to a drain terminal of the third transistor;
a sixth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the drain terminal of the fourth transistor for generating a level-shifted POR voltage signal;
a buffer connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal; and
a flip-flop having a data input terminal connected to the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal.
11. The integrated circuit of claim 10 , further comprising a processor connected to the output terminal of the flip-flop for receiving the voltage-monitor signal and determining a voltage level of the first supply voltage when the second supply voltage equals the POR de-assertion threshold, and wherein the processor further determines the POR de-assertion threshold based on the voltage level of the first supply voltage.
12. The integrated circuit of claim 11 , wherein the level-shifted POR voltage signal is generated at the voltage level of the first supply voltage.
13. The integrated circuit of claim 10 , wherein the voltage divider includes a resistor-ladder circuit having a voltage tap, wherein the second supply voltage is outputted at the voltage tap.
14. The integrated circuit of claim 10 , wherein the buffer comprises:
a first inverter connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal and generating an inverted level-shifted POR voltage signal; and
a second inverter connected to the first inverter for receiving the inverted level-shifted POR voltage signal and generating the delayed level-shifted POR voltage signal.
15. The integrated circuit of claim 14 , wherein the first inverter comprises:
a seventh transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal; and
an eighth transistor having a source terminal connected to ground, a gate terminal connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal, and a drain terminal connected to a drain terminal of the seventh transistor for outputting the inverted level-shifted POR voltage signal.
16. The integrated circuit of claim 15 , wherein the second inverter comprises:
a ninth transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the drain terminal of the seventh transistor for receiving the inverted level-shifted POR voltage signal; and
a tenth transistor having a source terminal connected to ground, a gate terminal connected to the drain terminal of the seventh transistor for receiving the inverted level-shifted POR voltage signal, and a drain terminal connected to a drain terminal of the ninth transistor for outputting the delayed level-shifted POR voltage signal.
17. The integrated circuit of claim 16 , wherein the first, fifth, sixth, seventh and ninth transistors are p-channel metal oxide semiconductor (PMOS) transistors, and wherein the second, third, fourth, eighth and tenth transistors are n-channel metal oxide semiconductor (NMOS) transistors.
18. An integrated circuit, comprising:
a voltage divider for receiving a first supply voltage and outputting a second supply voltage;
a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold;
an inverter connected to the POR circuit for receiving the POR voltage signal and generating an inverted POR voltage signal;
a level-shifter connected to the POR circuit and the inverter for receiving the POR voltage signal and the inverted POR voltage signal, respectively, and generating a level-shifted POR voltage signal;
a buffer connected to the level-shifter for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal;
a flip-flop having a data input terminal for receiving the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the level-shifter for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal; and
a processor, connected to the output terminal of the flip-flop for receiving the voltage-monitor signal, determining a voltage level of the first supply voltage when the second supply voltage equals the POR de-assertion threshold, and determining the POR de-assertion threshold based on the voltage level of the first supply voltage.
19. The integrated circuit of claim 18 , wherein the level-shifter comprises:
a first transistor having a source terminal connected to ground and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
a second transistor having a source terminal connected to ground and a gate terminal connected to the inverter for receiving the inverted POR voltage signal;
a third transistor having a source terminal connected to the first supply voltage, a gate terminal connected to a drain terminal of the second transistor, and a drain terminal connected to a drain terminal of the first transistor; and
a fourth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the drain terminal of the second transistor for outputting the level-shifted POR voltage signal.
20. The integrated circuit of claim 18 , wherein the buffer comprises:
a first transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the level-shifter for receiving the level-shifted POR voltage signal;
a second transistor having a source terminal connected to ground, a gate terminal connected to the level-shifter for receiving the level-shifted POR voltage signal and a drain terminal connected to a drain terminal of the first transistor for outputting the inverted level-shifted POR voltage signal;
a third transistor having a source terminal connected to the first supply voltage and a gate terminal connected to the drain terminal of the first transistor for receiving the inverted level-shifted POR voltage signal; and
a fourth transistor having a source terminal connected to ground, a gate terminal connected to the drain terminal of the first transistor for receiving the inverted level-shifted POR voltage signal, and a drain terminal connected to a drain terminal of the third transistor for outputting the delayed level-shifted POR voltage signal.