IP Library Granted Patent US 9,318,458
Granted Patent B2
US 9,318,458 · App. 14/800,934 · Granted Apr 19, 2016

Bump structure having a side recess and semiconductor structure including the same

Inventors: Chih-Horng Chang (Taipei, TW); Tin-Hao Kuo (Hsinchu, TW); Chen-Shien Chen (Zhubei, TW); Yen-Liang Lin (Taichung, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/13H01L24/14H01L24/16H01L24/81H01L2224/0401H01L2224/05572H01L2224/05599H01L2224/10145H01L2224/131H01L2224/13011H01L2224/13015H01L2224/13018H01L2224/13082H01L2224/13083H01L2224/13147H01L2224/1412H01L2224/14051H01L2224/14152H01L2224/14153H01L2224/16238H01L2224/81191H01L2224/81815H01L2924/00014H01L2924/01322H01L2924/2064Y10T428/12493Y10T428/24479
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Quick Facts
Patent No.
US 9,318,458
App. No.
14/800,934
Granted
Apr 19, 2016
Kind
B2
Abstract

A bump structure includes a first end; and a second end opposite the first end. The bump structure further includes a side connected between the first end and the second end, wherein the side comprises a recess for a reflowed solder material to fill, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end.

Claims (37)

1. A bump structure comprising:

a first end;

a second end opposite the first end;

a side connected between the first end and the second end, wherein the side comprises a recess, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end; and

wherein a depth of the recess into the bump structure ranges from about 0.5 μm to about 15 μm.

2. The bump structure of claim 1 , wherein the first surface is substantially planar and the second surface is substantially planar.

3. The bump structure of claim 2 , wherein the first surface directly contacts the second surface.

4. The bump structure of claim 2 , wherein the recess further defines a third surface connecting the first surface to the second surface.

5. The bump structure of claim 4 , wherein the third surface is substantially perpendicular to at least one of the first surface or the second surface.

6. The bump structure of claim 4 , wherein the third surface is a curved surface.

7. The bump structure of claim 4 , wherein a length of the third surface is equal to or less than about 30 microns (μm).

8. The bump structure of claim 1 , wherein a shape of the first end is different from a shape of the second end.

9. The bump structure of claim 1 , wherein a maximum distance between the first surface and the second surface ranges from about 8 μm to about 15 μm.

10. The bump structure of claim 1 , further comprising:

a solder layer;

a copper post layer arranged onto the solder layer, and

an under-bump metallurgy (UBM) layer arranged onto the copper post layer, wherein the recess is arranged within sidewalls of the solder layer, the copper post layer, and the UBM layer.

11. A semiconductor structure comprising:

a plurality of bump structures configured to electrically connect to a separate die, wherein each bump structure of the plurality of bump structures comprises:

a first end;

a second end opposite the first end; and

a side connected between the first end and the second end, wherein the side comprises a recess,

wherein a recess for a first bump structure of the plurality of bump structures is oriented in a first direction, and a recess for a second bump structure of the plurality of bump structures is oriented in a second direction different from the first direction.

12. The semiconductor structure of claim 11 , wherein the first direction is toward a closest center line of the semiconductor structure with respect to the first bump structure.

13. The semiconductor structure of claim 12 , wherein the second direction is toward the closest center line of the semiconductor structure with respect to the first bump structure.

14. The semiconductor structure of claim 11 , wherein the first direction is angled with respect to the second direction.

15. The semiconductor structure of claim 11 , wherein the first direction is perpendicular with respect to the second direction.

16. The semiconductor structure of claim 11 , wherein a recess for a third bump structure of the plurality of bump structures is oriented in a third direction different from the first direction and from the second direction.

17. The semiconductor structure of claim 11 , further comprising a plurality of non-recessed bump structures configured to electrically connect to the separate die.

18. The semiconductor structure of claim 17 , wherein the first bump structure is adjacent to at least one non-recessed bump structure of the plurality of non-recessed bump structures.

19. A semiconductor structure comprising:

a plurality of bump structures configured to electrically connect to a separate die, wherein each bump structure of the plurality of bump structures comprises:

a first end;

a second end opposite the first end; and

a side connected between the first end and the second end, wherein the side comprises a recess,

wherein a first end for a first bump structure of the plurality of bump structures is oriented a first direction, and a first end for a second bump structure of the plurality of bump structures is oriented a second direction different from the first direction.

20. The semiconductor structure of claim 19 , wherein the first direction is perpendicular with respect to the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2015
From: CHANG, CHIH-HORNG; KUO, TIN-HAO; CHEN, CHEN-SHIEN; LIN, YEN-LIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 036109/0913 →
Continuity (3)
Continuation 14507189 · Oct 6, 2014
Continuation In Part 13192302 · Jul 27, 2011
Related Publication 20150318253A1 · Nov 5, 2015