IP Library Granted Patent US 9,323,711
Granted Patent B2
US 9,323,711 · App. 14/682,926 · Granted Apr 26, 2016

Chip having port to receive value that represents adjustment to transmission parameter

Inventors: Mark A. Horowitz (Menlo Park, CA); Craig E. Hampel (Los Altos, CA); Alfredo Moncayo (Camarillo, CA); Kevin S. Donnelly (Los Altos, CA); Jared L. Zerbe (Woodside, CA)
Assignee: Rambus Inc.
G06F13/4243G06F3/061G06F3/0611G06F3/0619G06F3/0658G06F3/0661G06F3/0679G06F3/0688G06F12/0246G06F12/1081G06F13/102G06F13/1689G06F13/364G06F13/4072G06F13/4086G06F13/4234G11C5/04G11C5/063G11C7/1048G11C7/1072G11C7/222G11C16/32G11C19/00H03K19/00384H03K19/018585G06F2206/1014G06F2212/7201G11C7/22
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,323,711
App. No.
14/682,926
Granted
Apr 26, 2016
Kind
B2
Abstract

An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Claims (31)

1. A flash memory device, comprising:

memory for storing data;

a bidirectional port of a bus for receiving a parameter whose value varies in accordance with a count of devices on the bus to be driven via the bidirectional port, the parameter to set a transmission parameter of the flash memory device;

a register for storing a parameter control value corresponding to the parameter, received via the bidirectional port, whose value varies in accordance with the count of devices on the bus to be driven via the bidirectional port;

adjustment circuitry for setting the transmission parameter in accordance with the parameter control value; and,

an output driver, coupled to the bidirectional port for driving data via the bidirectional port, the data retrieved from the memory, the data to be driven in accordance with the parameter control value.

2. The flash memory device of claim 1 , wherein the parameter whose value varies in accordance with the count of devices on the bus to be driven via the bidirectional port is a count of the number of memory devices coupled to the bus.

3. The flash memory device of claim 1 , wherein the transmission parameter comprises a drive strength.

4. The flash memory device of claim 3 , wherein the drive strength comprises at least three different values.

5. The flash memory device of claim 1 , wherein the transmission parameter is selected from a group comprising at least drive strength, transmit timing, slew rate, and equalization of the output driver.

6. The flash memory device of claim 1 , wherein the transmission parameter affects a slew rate of signals to be driven by the output driver.

7. The flash memory device of claim 1 , wherein the parameter control value is to be selected based on a topology of memory devices on the bus to be driven by the output driver.

8. The flash memory device of claim 1 , wherein the bidirectional port of the bus is for receiving, in an access request, the parameter whose value varies in accordance with the count of devices on the bus.

9. A method of operating a flash memory device having memory for storing data, comprising:

receiving, via a bidirectional port, a parameter control value corresponding to a feature of the flash device the parameter control value set in accordance with a count of memory devices on a bus to be driven via the bidirectional port;

storing the parameter control value in a register;

setting a transmission parameter in accordance with the parameter control value; and

in accordance with the transmission parameter, driving, via the bidirectional port, data retrieved from the memory.

10. The method of claim 9 , wherein the transmission parameter comprises a selected drive strength.

11. The method of claim 10 , wherein at least three different values may be selected as the selected drive strength.

12. The method of claim 9 , wherein the feature is selected from a group comprising at least drive strength, transmit timing, slew rate, and equalization.

13. The method of claim 9 , wherein the transmission parameter affects a slew rate of the driving of the data retrieved from the memory.

14. The method of claim 9 , wherein the parameter control value is to be selected based on a topology of the bus to be driven via the bidirectional port.

15. A flash memory device, comprising:

means to receive, from a bidirectional bus, a parameter control value corresponding to a feature of the flash memory device, the parameter control value set in accordance with a count of memory devices on the bidirectional bus to be driven via the bidirectional port;

means to store the parameter control value; and

means for driving data retrieved from memory, the data to be driven in accordance with a transmission parameter determined by the parameter control value, the data being driven on the bidirectional bus.

16. The flash memory device of claim 15 , wherein the transmission parameter corresponds to a selected drive strength.

17. The flash memory device of claim 16 , wherein at least three different values may be selected as the selected drive strength.

18. The flash memory device of claim 15 , wherein the transmission parameter affects a slew rate of the means for driving.

19. The flash memory device of claim 15 , wherein the parameter control value is to be selected based on a topology of memory devices on the bidirectional bus.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: HOROWITZ, MARK A.; BARTH, RICHARD M.; HAMPEL, CRAIG E.; MONCAYO, ALFREDO; DONNELLY, KEVIN S.; ZERBE, JARED L.
To: RAMBUS INC.
Reel/Frame 035424/0548 →
Continuity (14)
Continuation 14321718 · Jul 1, 2014
Continuation 13853978 · Mar 29, 2013
Continuation 13535228 · Jun 27, 2012
Continuation 13196840 · Aug 2, 2011
Continuation 12479679 · Jun 5, 2009
Continuation 11929974 · Oct 30, 2007
Continuation 11672018 · Feb 6, 2007
Continuation 11181411 · Jul 13, 2005
Continuation 11073403 · Mar 4, 2005
Continuation 10742247 · Dec 19, 2003
Continuation 10359061 · Feb 4, 2003
Continuation 09910217 · Jul 19, 2001
Continuation 09420949 · Oct 19, 1999
Related Publication 20150212954A1 · Jul 30, 2015