Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.
1. A method of fabricating doped FET and an undoped FET by using a blocking stack in a replacement metal gate process, the method comprising:
(a) forming first opening in a dielectric layer overlying a first FET region of a substrate and forming a second opening in a dielectric layer overlying a second FET region of the substrate;
(b) forming a high-k layer lining both the first and second openings;
(c) forming a blocking stack over the second FET region;
(d) removing a portion the blocking stack to leave a thinned remaining portion of the stack over the second FET region;
(e) forming a doping stack over the first and second FET regions of the substrate and annealing the substrate to form a doped high-k in the first FET region while the high-k of the second FET region remains undoped;
(f) forming a first work function metal stack in the first opening of the first FET region;
(g) forming a second work function metal stack in the second opening of the second FET region; and
(h) filling the first and second openings with a fill material.
2. The method of claim 1 wherein the blocking stack is a multi-layered blocking stack.
3. The method of claim 1 wherein the blocking stack includes a first bottom layer, a second middle layer, and a third top layer.
4. The method of claim 3 wherein the first bottom layer and the third top layer are the same type of material.
5. The method of claim 4 wherein the first bottom layer and the third top layer are titanium nitride.
6. The method of claim 3 wherein the second middle layer contains lanthanum.
7. The method of claim 3 wherein (d) removing a portion the blocking stack further comprises:
etching the top layer selectively to the middle layer using a peroxide containing solution to expose the middle layer; and
etching the exposed middle layer selective to the bottom layer to expose the bottom layer wherein the exposed bottom layer has a thickness from about 15 angstroms to about 25 angstroms.
8. The method of claim 1 wherein the blocking layer is a single layer.
9. The method of claim 1 wherein the blocking layer comprises titanium nitride.
10. The method of claim 9 wherein (d) removing the portion of the blocking stack to leave the thinned remaining portion of the stack over the second FET region further comprises:
exposing the blocking stack to a solution comprising about a 50:1.5 aqueous solution of ammonium hydroxide and hydrogen peroxide at a temperature equal to or less than about 25 C.
11. The method of claim 9 wherein (d) removing the portion of the blocking stack to leave the thinned remaining portion of the stack over the second FET region further comprises:
removing the portion of the blocking stack at a removal rate of about 5-10 angstroms per minute.
12. The method of claim 1 wherein (c) forming the blocking stack over the second FET region further comprises:
forming the blocking stack over the first and second FET regions of the substrate;
forming a soft mask lithography stack including an optical planarization layer;
exposing and developing the soft mask lithography stack; and
patterning the optical planarization layer to remove the optical planarization over the first FET region while the blocking stack protects the high-k layer in the first opening.