Methods of forming a semiconductor circuit element and semiconductor circuit element
The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.
1. A method of forming a semiconductor circuit element, the method comprising:
providing a first semiconductor device having a first gate structure disposed over a first active region which is provided within a semiconductor substrate, said first gate structure comprising a first spacer structure and a first dummy gate structure;
providing a second semiconductor device having a second gate structure disposed over a second active region adjacent to said first active region, wherein said second gate structure comprises a second dummy gate electrode material, a second spacer structure and a second gate oxide structure which comprises a TiN layer disposed on a high-k material different from said ferroelectric high-k material;
after providing the second semiconductor device, replacing said first dummy gate structure by a first gate oxide structure and a first gate electrode material, wherein said first gate oxide structure comprises a ferroelectric high-k material; and
after the replacement of said first dummy gate structure in said first semiconductor device, replacing said second dummy gate electrode material by a second gate electrode material.
2. The method of claim 1 , wherein replacing said first dummy gate structure comprises removing said first dummy gate structure for forming a gate trench in said first gate structure and depositing said ferroelectric high-k material over said first semiconductor device and in said gate trench and on and in contact with a surface of the semiconductor substrate.
3. The method of claim 2 , further comprising depositing a TiN layer on and in contact with said ferroelectric high-k material.
4. The method of claim 2 , wherein said ferroelectric high-k material is deposited by performing an ALD process.
5. The method of claim 1 , wherein said first dummy gate structure comprises an insulating material layer and a first dummy gate electrode material disposed on said insulating material layer, said insulating material layer comprising at least one of a TiN material and a high-k dielectric material.
6. The method of claim 5 , wherein replacing said first dummy gate structure comprises performing one of a selective RIE process and a wet etch process with said insulating material layer as an etch stop and performing a further wet etch process to completely remove said insulating material layer.
7. The method of claim 1 , wherein the replacement of said second dummy gate electrode material in said second semiconductor device comprises performing a selective etching process by using said second gate oxide structure as an etch stop.
8. The method of claim 7 , further comprising, prior to the replacement of said first dummy gate structure in said first semiconductor device, forming a first masking pattern for covering said second semiconductor device during the replacement of said first dummy gate structure in said first semiconductor device.
9. The method of claim 8 , further comprising, after the replacement of said first dummy gate structure in said first semiconductor device, forming a second masking pattern for covering said first semiconductor device during the replacement of said second dummy gate electrode material.
10. The method of claim 1 , wherein said first semiconductor device is provided as one of a PMOS device and an NMOS device and said second semiconductor device is provided as an NMOS device when said first semiconductor device is provided as a PMOS device and said second semiconductor device is provided as a PMOS device when said first semiconductor device is provided as an NMOS device.
11. A method of forming a semiconductor circuit element, the method comprising:
providing a first semiconductor device having a first gate structure disposed over a first active region which is provided within a semiconductor substrate, said first gate structure comprising a first spacer structure and a dummy gate structure;
providing a second semiconductor device having a second gate structure disposed over a second active region adjacent said first active region, wherein said second gate structure comprises a dummy gate electrode material, a second spacer structure and a first gate oxide structure which comprises a TiN layer disposed on a high-k material;
forming a first masking pattern for covering said second semiconductor device and exposing said first semiconductor device;
replacing said dummy gate structure by a first gate electrode material and a second gate oxide structure, wherein said second gate oxide structure comprises a ferroelectric high-k material different from said high-k material of said second semiconductor device;
removing said first masking pattern;
forming a second masking pattern for covering said first semiconductor device and exposing said second semiconductor device; and
replacing said dummy gate electrode material by a second gate electrode material.
12. The method of claim 11 , wherein said first semiconductor device and said second semiconductor device form a CMOS device.
13. A method of forming a semiconductor circuit element, the method comprising:
providing a first semiconductor device having a first gate structure disposed over a first active region which is provided within a semiconductor substrate, said first gate structure comprising a first spacer structure and a first dummy gate structure; and
replacing said first dummy gate structure by a first gate oxide structure and a first gate electrode material, wherein said first gate oxide structure comprises a ferroelectric high-k material and wherein replacing said first dummy gate structure comprises removing said first dummy gate structure for forming a gate trench in said first gate structure and depositing said ferroelectric high-k material over said first semiconductor device and in said gate trench and on and in contact with a surface of the semiconductor substrate.
14. The method of claim 13 , further comprising depositing a TiN layer on said ferroelectric high-k material.
15. A method of forming a semiconductor circuit element, the method comprising:
providing a first semiconductor device having a first gate structure disposed over a first active region which is provided within a semiconductor substrate, said first gate structure comprising a first spacer structure and a first dummy gate structure; wherein said first dummy gate structure comprises an insulating material layer and a first dummy gate electrode material disposed on said insulating material layer, said insulating material layer comprising at least one of a TiN material and a high-k dielectric material, and
replacing said first dummy gate structure by a first gate oxide structure and a first gate electrode material, wherein said first gate oxide structure comprises a ferroelectric high-k material.
16. The method of claim 15 , wherein replacing said first dummy gate structure comprises removing said first dummy gate structure for forming a gate trench in said first gate structure and depositing said ferroelectric high-k material over said first semiconductor device and in said gate trench and on and in contact with a surface of the semiconductor substrate.
17. The method of claim 16 , further comprising depositing a TiN layer on said ferroelectric high-k material.
18. The method of claim 15 , wherein replacing said first dummy gate structure comprises performing one of a selective RIE process and a wet etch process with said insulating material layer as an etch stop and performing a further wet etch process to completely remove said insulating material layer.