Stress buffer structures in a mounting structure of a semiconductor device
A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad. Additionally, the semiconductor device includes a stress buffer layer over the passivation layer where the stress buffer layer exposes a portion of the bonding pad, and where a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad. Furthermore, the semiconductor device includes an under-bump metallurgy (UBM) layer over the stress buffer layer, where the UBM layer contacts a portion of the bonding pad.
1. A semiconductor device, comprising:
a bonding pad on a substrate;
a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad;
a stress buffer layer over the passivation layer, the stress buffer layer exposing a portion of the bonding pad, wherein a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad; and
an under-bump metallurgy (UBM) layer over the stress buffer layer, wherein the UBM layer contacts a portion of the bonding pad,
wherein the bonding pad comprises a stepwise configuration which at least partially defines a stepwise sidewall of the stress buffer layer.
2. The semiconductor device according to claim 1 , wherein the stress buffer polymer layer comprises polyimide, polybenzoxazole (PBO), epoxy-based polymers, phenol-based polymers, or benzocyclobutene (BCB).
3. The semiconductor device of claim 1 , wherein the wall of the stress buffer layer comprises an upper step and a lower step, wherein the upper step and the lower step have equal lengths.
4. The semiconductor device of claim 1 , wherein the wall of the stress buffer layer comprises an upper step and a lower step, wherein the upper step has a first length that is greater than a second length of the lower step.
5. The semiconductor device of claim 1 , further comprising a sidewall of the passivation layer conforming to the contours of the wall of the stress buffer layer.
6. The semiconductor device of claim 1 , further comprising the UBM layer conforming to the contours of the wall of the stress buffer layer.
7. A semiconductor device, comprising:
a bonding pad on a substrate;
a stress buffer structure over the bonding pad, the stress buffer structure exposing a portion of the bonding pad, wherein the stress buffer structure comprises a stepped wall that extends upwardly from the exposed portion of the bonding pad; and
an under-bump metallurgy (UBM) layer over the bonding pad, wherein the UBM layer contacts a portion of the bonding pad;
wherein the bonding pad comprises a stepwise configuration which at least partially defines a stepwise sidewall of the stress buffer layer.
8. The semiconductor device according to claim 7 , wherein the stress buffer polymer layer comprises polyimide, polybenzoxazole (PBO), epoxy-based polymers, phenol-based polymers, or benzocyclobutene (BCB).
9. The semiconductor device of claim 7 , further comprising a passivation layer surrounding sidewalls of the bonding pad.
10. The semiconductor device of claim 9 , wherein a sidewall of the passivation layer conforms to the contours of the stepped wall of the stress buffer structure.
11. The semiconductor device of claim 7 , wherein the UBM layer conforms to the contours of the stepped wall of the stress buffer layer.
12. The semiconductor device of claim 7 , further comprising a solder bump over the UBM layer.