IP Library › Granted Patent US 9,343,399
Granted Patent B2
US 9,343,399 · App. 14/149,530 · Granted May 17, 2016

Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology

Inventors: Je-Hsiung Lan (San Diego, CA); Chengjie Zuo (Santee, CA); Changhan Hobie Yun (San Diego, CA); Jonghae Kim (San Diego, CA); Daeik Daniel Kim (San Diego, CA); Mario Francisco Velez (San Diego, CA); Robert Paul Mikulka (Oceanside, CA); Niranjan Sunil Mudakatte (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H01L23/49822H01L23/5222H01L23/5227H01L23/642H01L27/016H01L28/60H01L23/645H01L27/0805H01L28/10H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,343,399
App. No.
14/149,530
Granted
May 17, 2016
Kind
B2
Abstract

An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Claims (28)

1. An integrated circuit device, comprising:

a substrate;

a first interlayer dielectric layer on the substrate comprising a first conductive layer and a second conductive layer;

a first conductive stack comprising a third conductive layer coupled to a portion of the first conductive layer in which a first via couples the third conductive layer to the portion of the first conductive layer, in which the first conductive stack is not isolated from the substrate;

a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate; and

a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

2. The integrated circuit device of claim 1 , further comprising:

a third conductive stack comprising the third conductive layer coupled to a portion of the first conductive layer with a second via.

3. The integrated circuit device of claim 2 , further comprising:

a seed layer on the first interlayer dielectric layer that is coupled to the first conductive layer.

4. The integrated circuit device of claim 1 , in which the first conductive layer and the second conductive layer comprise at least a first plate and a second plate of a metal-insulator-metal (MIM) capacitor.

5. The integrated circuit device of claim 1 , further comprising:

a seed layer on the first interlayer dielectric layer that is coupled to the second conductive layer.

6. The integrated circuit device of claim 1 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

7. An integrated circuit device, comprising:

a substrate;

a first interlayer dielectric layer on the substrate comprising a first conductive means and a second conductive means;

a first conductive stack comprising a third conductive means coupled to a portion of the first conductive means, in which a first via couples the third conductive means to the portion of the first conductive means, in which the first conductive stack is not isolated from the substrate;

a second conductive stack comprising a fourth conductive means directly on a portion of the third conductive means that is isolated from the substrate; and

a second interlayer dielectric layer surrounding the third conductive means and the fourth conductive means.

8. The integrated circuit device of claim 7 , further comprising:

a third conductive stack comprising the third conductive means coupled to a portion of the first conductive means with a second via.

9. The integrated circuit device of claim 8 , further comprising:

a seed layer on the first interlayer dielectric layer that is coupled to the first conductive means.

10. The integrated circuit device of claim 7 , in which the first conductive means and the second conductive means comprise at least a first plate and a second plate of a metal-insulator-metal (MIM) capacitor.

11. The integrated circuit device of claim 7 , further comprising:

a seed layer on the first interlayer dielectric layer that is coupled to the second conductive means.

12. The integrated circuit device of claim 7 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2014
From: LAN, JE-HSIUNG; ZUO, CHENGJIE; YUN, CHANGHAN HOBIE; KIM, JONGHAE; KIM, DAEIK DANIEL; VELEZ, MARIO FRANCISCO; MIKULKA, ROBERT PAUL; MUDAKATTE, NIRANJAN SUNIL
To: QUALCOMM INCORPORATED
Reel/Frame 032023/0805 →
Continuity (2)
Provisional Application 61845573 · Jul 12, 2013
Related Publication 20150014812A1 · Jan 15, 2015