Semiconductor testing jig and semiconductor testing method performed by using the same
A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.
1. A semiconductor testing jig that fixes a measurement target while it is held between a chuck stage and said measurement target,
the semiconductor testing jig comprising a base on which said measurement target is to be installed and which can be attached to said chuck stage,
the base including:
a first main surface to become an installation surface for said measurement target;
a second main surface opposite said first main surface and which is to contact said chuck stage;
a plurality of porous regions each containing a porous member, the porous regions being provided selectively as seen in plan view, and penetrating through said base from said first main surface toward said second main surface; and
a nonporous region provided between said plurality of porous regions as seen in plan view.
2. The semiconductor testing jig according to claim 1 , wherein each porous member extends from said first main surface toward said second main surface to fill in each porous region to a predetermined depth.
3. The semiconductor testing jig according to claim 1 , wherein the thickness of each porous member is increased with smaller distances of said porous regions from the center of said base.
4. The semiconductor testing jig according to claim 1 , wherein said second main surface includes an O-ring groove in which an O-ring is to be fitted.
5. The semiconductor testing jig according to claim 1 , wherein each porous region filled with said porous member has a surface facing said second main surface and formed into a concave shape.
6. A semiconductor testing jig that fixes a measurement target while it is held between a chuck stage and said measurement target,
the semiconductor testing jig comprising a base on which said measurement target is to be installed and which can be attached to said chuck stage,
the base including:
a first main surface to become an installation surface for said measurement target;
a second main surface opposite said first main surface and which is to contact said chuck stage; and
a porous region containing a porous member, the porous region being provided selectively as seen in plan view, and penetrating through said base from said first main surface toward said second main surface,
wherein an end neighboring part of said first main surface of said base is beveled.
7. A semiconductor testing jig that fixes a measurement target while it is held between a chuck stage and said measurement target,
the semiconductor testing jig comprising a base on which said measurement target is to be installed and which can be attached to said chuck stage,
the base including:
a first main surface to become an installation surface for said measurement target;
a second main surface opposite said first main surface and which is to contact said chuck stage;
a porous region containing a porous member, the porous region being provided selectively as seen in plan view, and penetrating through said base from said first main surface toward said second main surface; and
an auxiliary member attached to a side surface of said base so as to surround the base.
8. The semiconductor testing jig according to claim 7 , wherein said auxiliary member is different in thickness from said base.
9. The semiconductor testing jig according to claim 1 , further comprising an auxiliary member attached to a side surface of said base so as to surround the base,
wherein said auxiliary member includes an O-ring groove in which an O-ring is to be fitted, the O-ring groove being formed in a surface of said auxiliary member to contact said chuck stage.
10. A semiconductor testing method performed by using a semiconductor testing jig that fixes a measurement target while it is held between a chuck stage and said measurement target,
the semiconductor testing jig comprising a base on which said measurement target is to be installed and which can be attached to said chuck stage,
the base including:
a first main surface to become an installation surface for said measurement target;
a second main surface opposite said first main surface and which is to contact said chuck stage; and
a porous region containing a porous member, the porous region being provided selectively as seen in plan view, and penetrating through said base from said first main surface toward said second main surface;
the semiconductor testing method comprising the steps of:
(a) installing said semiconductor testing jig on said chuck stage;
(b) installing said measurement target on said semiconductor testing jig;
(c) vacuum sucking said measurement target onto said semiconductor testing jig; and
(d) measuring the electrical characteristics of said measurement target.
11. The semiconductor testing method according to claim 10 , further comprising the steps of
(e) preparing a plurality of said semiconductor testing jigs with porous members of different thicknesses to fill in porous regions, the step (e) being performed before said step (a), and
(f) selecting one of said semiconductor testing jigs in response to the thickness of said measurement target, the step (f) being performed before said step (a).