Semiconductor device with transistor local interconnects
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.
1. A semiconductor device comprising:
a semiconductor substrate;
a first transistor and a second transistor disposed on said substrate;
each of said transistors comprising a source, a drain, and a gate;
a first CB layer electrically connected to said gate of said first transistor;
a second CB layer electrically connected to said gate of said second transistor; and
a CA layer extending longitudinally between a first end and a second end; wherein
said first CB layer is electrically connected to said first end of said CA layer;
said second CB layer is electrically connected to said second end of said CA layer;
said gate of said first transistor extends longitudinally along a first line and said gate of said second transistor extends longitudinally along a second line, wherein said first and second lines are generally parallel to one another and spaced apart from one another; and
said CA layer extends generally parallel to said lines and generally perpendicular to said first CB layer and said second CB layer; and
wherein said first CB layer extends longitudinally beyond said gate of said first transistor and/or said second CB layer extends longitudinally beyond said gate of said second transistor.
2. A semiconductor device as set forth in claim 1 wherein said CA layer is disposed between said gates.
3. A semiconductor device as set forth in claim 2 wherein said CA layer defines a length extending parallel to said lines greater than a length of said CB layers extending parallel to said lines.
4. A semiconductor device as set forth in claim 3 further comprising a third transistor having a gate extending longitudinally along said first line and a fourth transistor having a gate extending longitudinally along said second line.
5. A semiconductor device as set forth in claim 4 wherein said gates of said first and third transistors are separated by a gap and said gates of said second and fourth transistors are separated by gap.
6. A semiconductor device as set forth in claim 5 wherein said CA layer extends across said gap.
7. A semiconductor device as set forth in claim 1 wherein said CA layer extends less than 110 nanometers above said substrate.