IP Library Granted Patent US 9,362,203
Granted Patent B2
US 9,362,203 · App. 14/499,162 · Granted Jun 7, 2016

Staged via formation from both sides of chip

Inventors: Vage Oganesian (Sunnyvale, CA); Belgacem Haba (Saratoga, CA); Ilyas Mohammed (Santa Clara, CA); Craig Mitchell (San Jose, CA); Piyush Savalia (San Jose, CA)
Assignee: Tessera, Inc.
H01L23/481H01L21/76898H01L23/50H01L24/03H01L24/05H01L25/0657H01L25/50H01L2224/0401H01L2224/05009H01L2224/06181H01L2224/16145H01L2224/32145H01L2224/73204H01L2225/06513H01L2225/06541H01L2924/01322H01L2924/07811H01L2924/12042
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Quick Facts
Patent No.
US 9,362,203
App. No.
14/499,162
Filed
Sep 27, 2014
Granted
Jun 7, 2016
Kind
B2
Art Unit
2897
USPC
257/774
Abstract

A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

Claims (15)

1. A semiconductor assembly, comprising:

a semiconductor element having a front surface, a rear surface remote from the front surface, and an opening extending from the rear surface partially through the thickness of the semiconductor element, the semiconductor element further including a plurality of conductive pads at the front surface, and

a hole extending through the conductive pads and partially through the thickness of the semiconductor element, the hole meeting the opening at a location between the front and rear surfaces, wherein at the location where the hole and the opening meet, interior surfaces of the hole and the opening extend at different angles relative to the rear surface such that there is a step change between slopes of the interior surfaces of the hole and the opening;

a continuous dielectric layer partially overlying the respective conductive pads at a location above the respective conductive pads and overlying an interior surface of the semiconductor material within the hole and the opening;

a conductive element electrically contacting the conductive pads, the conductive element having a first portion exposed at the rear surface for electrical connection with an external device, the conductive element having a second portion overlying the continuous dielectric layer;

wherein the first portion of the conductive element having a first internal space filled with a dielectric region within the opening and the second portion of the conductive element having a second internal space within the hole; and

an outer surface of the dielectric region is located above but parallel to a plane defined by the rear surface and located below a plane defined a contact surface of the first portion of the conductive element exposed at the rear surface.

2. A semiconductor assembly as claimed in claim 1 , wherein the conductive pads have an outwardly facing surface facing away from the semiconductor element, wherein at least a portion of the dielectric layer contacts the outwardly-facing surface.

3. A semiconductor assembly as claimed in claim 1 , wherein the conductive element includes a conductive interconnect coupled to the conductive pad and a conductive contact coupled to the conductive interconnect, the conductive contact being exposed at the rear surface.

4. A semiconductor assembly as claimed in claim 3 , wherein the opening has a first width in a lateral direction along the rear surface, and the conductive contact has a second width in the lateral direction, the first width being greater than the second width.

5. A semiconductor assembly as claimed in claim 1 , wherein the semiconductor element includes a plurality of active semiconductor devices and the plurality of conductive pads are electrically connected with at least one of the plurality of active semiconductor devices.

6. A semiconductor assembly as claimed in claim 1 , wherein the conductive pads have an outwardly facing surface facing away from the semiconductor element, wherein at least a portion of the at least one conductive element overlies the outwardly-facing surface and is electrically connected thereto.

7. A semiconductor assembly as claimed in claim 1 , wherein the conductive element includes a conductive interconnect exposed at the rear surface for electrical connection to an external device, the conductive interconnect extending into the opening, and a conductive via, extending within the hole and coupled to the conductive interconnect and the conductive pads.

8. A semiconductor assembly as claimed in claim 7 , wherein the conductive interconnect overlies an inner surface of the opening, the conductive interconnect conforming to a contour of the opening.

9. A semiconductor assembly as claimed in claim 8 , wherein the conductive interconnect extends along a portion of the inner surface of the opening.

Assignments (7)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2015
From: TESSERA RESEARCH LLC
To: TESSERA, INC.
Reel/Frame 034824/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2014
From: OGANESIAN, VAGE; HABA, BELGACEM; MOHAMMED, ILYAS; MITCHELL, CRAIG; SAVALIA, PIYUSH
To: TESSERA RESEARCH LLC
Reel/Frame 033914/0957 →
Continuity (2)
Division 12884649 · Sep 17, 2010
Related Publication 20150130077A1 · May 14, 2015