IP Library › Granted Patent US 9,362,234
Granted Patent B2
US 9,362,234 · App. 14/149,335 · Granted Jun 7, 2016

Shielded device packages having antennas and related fabrication methods

Inventors: Eduard J. Pabst (Mesa, AZ); Sergio P. Pacheco (Scottsdale, AZ); Weng F. Yap (Chandler, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H01L23/552H01L21/768H01L23/3128H01L24/19H01L21/568H01L23/49816H01L23/5389H01L23/66H01L2223/6677H01L2224/12105
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Quick Facts
Patent No.
US 9,362,234
App. No.
14/149,335
Granted
Jun 7, 2016
Kind
B2
Abstract

Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.

Claims (51)

1. A device package comprising:

one or more electrical components;

a molding compound overlying the one or more electrical components;

a conductive interconnect structure within the molding compound; a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure; and

a shielding structure overlying the one or more electrical components, wherein:

the shielding structure is electrically connected to the frame structure;

at least a portion of the molding compound resides between the shielding structure and the one or more electrical components;

the shielding structure contacts a first surface of the frame structure; and

the first surface of the frame structure is aligned with a second surface of the portion of the molding compound.

2. The device package of claim 1 , wherein a third surface of the interconnect structure is aligned with the first surface and the second surface.

3. The device package of claim 1 , wherein the shielding structure comprises a planar structure having an opening aligned with the interconnect structure.

4. The device package of claim 1 , wherein an intermediate portion of the frame structure resides between the interconnect structure and the one or more electrical components.

5. The device package of claim 4 , the intermediate portion of the frame structure defining a first enclosed region and a second enclosed region, wherein:

the interconnect structure resides within the first enclosed region; and

the one or more electrical components reside within the second enclosed region.

6. The device package of claim 1 , wherein the shielding structure contacts the frame structure.

7. The device package of claim 1 , wherein the interconnect structure is electrically isolated from the shielding structure.

8. The device package of claim 1 , wherein:

the shielding structure includes an opening concentrically aligned with the interconnect structure; and

a circumference of the opening is greater than a circumference of the interconnect structure.

9. The device package of claim 1 , further comprising an antenna structure overlying the shielding structure, wherein the antenna structure is electrically connected to the interconnect structure.

10. The device package of claim 9 , further comprising a dielectric material overlying the shielding structure, wherein the antenna structure overlies the dielectric material.

11. The device package of claim 10 , further comprising a via within the dielectric material, the via overlying the interconnect structure, wherein the antenna structure is electrically coupled to the via.

12. The device package of claim 1 , further comprising:

a routing structure, wherein the one or more electrical components, the frame structure, the interconnect structure, and the molding compound overlie the routing structure; and

a connection structure to receive a reference voltage, wherein the routing structure provides a first electrical connection between the connection structure and the frame structure.

13. The device package of claim 12 , further comprising an antenna structure overlying the shielding structure, wherein:

the antenna structure is electrically connected to the interconnect structure; and

the interconnect structure provides a second electrical connection between the routing structure and the antenna structure.

14. The device package of claim 1 , wherein:

a second portion of the molding compound resides laterally between the frame structure and the one or more electrical components; and

the frame structure resides laterally between the second portion of the molding compound and a third portion of the molding compound.

15. A method of fabricating a device package, the method comprising:

providing a frame structure circumscribing one or more electrical components, the frame structure having a first surface;

forming a molding compound overlying the one or more electrical components, the molding compound having a second surface aligned with the first surface, wherein a first portion of the molding compound resides between the frame structure and the one or more electrical components;

forming an interconnect structure within the molding compound, the frame structure circumscribing the interconnect structure; and

providing a shielding structure overlying the one or more electrical components, wherein the shielding structure is electrically connected to the frame structure and a second portion of the molding compound resides between the one or more electrical components and the shielding structure.

16. The method of claim 15 , further comprising forming an antenna structure overlying the shielding structure, wherein the antenna structure is electrically connected to the interconnect structure.

17. The method of claim 16 , further comprising:

forming a dielectric layer overlying the shielding structure and the interconnect structure; and

forming a conductive via within the dielectric layer, the conductive via contacting at least a portion of the interconnect structure, wherein forming the antenna structure comprises forming a conductive material on the dielectric layer, the conductive material being patterned to provide an electrical connection to the conductive via.

18. The method of claim 16 , further comprising:

forming a routing structure on the frame structure and the one or more electrical components; and

forming a connection interface for receiving a ground reference voltage on the routing structure, wherein the routing structure is configured to provide a first electrical connection between the interconnect structure and an interface of an electrical component of the one or more electrical components and a second electrical connection between the frame structure and the connection interface.

19. A device package comprising:

one or more electrical components;

a molding compound overlying the one or more electrical components, the molding compound having a planar upper surface;

a conductive interconnect structure within the molding compound, the interconnect structure having a first surface aligned with the planar upper surface of the molding compound;

a conductive frame structure circumscribing the one or more electrical components and the interconnect structure, the frame structure having a second surface aligned with the planar upper surface of the molding compound, at least a first portion of the molding compound residing laterally between the frame structure and the one or more electrical components and a second portion of the molding compound circumscribes the frame structure;

a shielding structure overlying the one or more electrical components, the shielding structure contacting the second surface of the frame structure and at least a third portion of the molding compound residing between the shielding structure and the one or more electrical components; and

an antenna structure overlying the shielding structure, wherein the antenna structure is electrically coupled to the interconnect structure.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2014
From: PABST, EDUARD J.; PACHECO, SERGIO P.; YAP, WENG F.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 031907/0663 →
Continuity (1)
Related Publication 20150194388A1 · Jul 9, 2015