IP Library Granted Patent US 9,363,450
Granted Patent B2
US 9,363,450 · App. 14/468,242 · Granted Jun 7, 2016

Imaging systems and methods for image signal gain adjustment

Inventors: Junichi Nakamura (Tokyo, JP); Shinichiro Matsuo (Kawasaki, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/3559H01L27/14609H04N5/3575H04N5/378H04N5/37452H04N5/35572
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Quick Facts
Patent No.
US 9,363,450
App. No.
14/468,242
Granted
Jun 7, 2016
Kind
B2
Abstract

An imaging system may include image processing circuitry and an image sensor having a pixel, readout circuitry, and control circuitry. The pixel may have a dual conversion gain gate for switching between a high conversion gain mode and a low conversion gain mode. The pixel may capture a first image signal while the dual conversion gain gate is turned of and a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on. The readout circuitry may identify a selected one of the first and second image signals to output to the image processing circuitry based on the first image signal. In this way, the readout circuitry may output a low conversion gain signal when saturating charge is stored on the charge storage region and may output a high conversion gain signal when insufficient charge is stored on the charge storage region.

Claims (38)

1. A method of operating an image sensor coupled to image processing circuitry, wherein the image sensor comprises an array of image sensor pixels and readout circuitry, the method comprising:

with an image sensor pixel in the array, capturing a first image signal while a dual conversion gain gate in the image sensor pixel is turned off;

with the image sensor pixel, capturing a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on;

with a memory circuit in the readout circuitry, storing the first image signal;

with the readout circuitry, identifying a selected one of the first and second image signals to output to the image processing circuitry based on the captured first image signal, wherein identifying the selected one of the first and second image signals to output to the image processing circuitry comprises:

determining whether the first image signal exceeds a predetermined threshold; and

in response to determining that the first image signal does not exceed the predetermined threshold, labeling the first image signal with an indication bit that instructs the readout circuitry not to overwrite the first image signal on the memory circuit; and

with the readout circuitry, outputting the identified image signal to the image processing circuitry.

2. The method defined in claim 1 , wherein the image sensor further comprises control circuitry, the method further comprising:

with the control circuitry, asserting a dual conversion gain control signal provided to the dual conversion gain gate to turn on the dual conversion gain gate after the image sensor pixel has captured the first image signal.

3. The method defined in claim 1 , wherein identifying the selected one of the first and second image signals to output to the image processing circuitry further comprises:

in response to determining that the first image signal does not exceed the predetermined threshold, outputting the first image signal to the image processing circuitry.

4. The method defined in claim 1 , wherein identifying the selected one of the first and second image signals to output to the image processing circuitry further comprises:

in response to determining that the first image signal exceeds the predetermined threshold, overwriting the first image signal on the memory circuit with the second image signal.

5. The method defined in claim 4 , wherein identifying the selected one of the first and second image signals to output to the image processing circuitry further comprises:

in response to determining that the first image signal exceeds the predetermined threshold, labeling the first image signal with an indication bit that instructs the readout circuitry to overwrite the first image signal on the memory circuit with the second image signal.

6. The method defined in claim 1 , wherein the first image signal comprises a first reset-level signal and a first image-level signal, the method further comprising:

with the readout circuitry, sampling the first reset-level signal onto sample and hold circuitry;

with analog-to-digital converter circuitry on the readout circuitry, converting the first reset-level signal into a first digital reset-level signal subsequent to sampling the first reset-level signal onto the sample and hold circuitry;

with the readout circuitry, sampling the first image-level signal onto the sample and hold circuitry subsequent to converting the first reset-level signal into the first digital reset-level signal; and

with the analog-to-digital converter circuitry, converting the first image-level signal into a first digital image-level signal subsequent to sampling the first image-level signal onto the sample and hold circuitry.

7. The method defined in claim 6 , wherein the second image signal comprises a second reset-level signal and a second image-level signal, the method further comprising:

with the readout circuitry, sampling the second image-level signal onto the sample and hold circuitry;

with the analog-to-digital converter circuitry, converting the second image-level signal into a second digital image-level signal subsequent to sampling the second image-level signal onto the sample and hold circuitry;

with the readout circuitry, sampling the second reset-level signal onto the sample and hold circuitry subsequent to converting the second image-level signal into the second digital reset-level signal;

with the analog-to-digital converter circuitry, converting the second reset-level signal into a second digital image-level signal subsequent to sampling the second reset-level signal onto the sample and hold circuitry.

8. The method defined in claim 7 , further comprising:

with the readout circuitry, outputting the first image signal to the image processing circuitry without outputting the second image signal.

9. A method of operating an image sensor coupled to image processing circuitry, wherein the image sensor comprises an array of image sensor pixels and readout circuitry, the method comprising:

with an image sensor pixel in the array, capturing a first image signal while a dual conversion gain gate in the image sensor pixel is turned off;

with the image sensor pixel, capturing a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on;

with a memory circuit in the readout circuitry, storing first image signal;

with the readout circuitry, identifying a selected one of the first and second image signals to output to the image processing circuitry based on the captured first image signal, wherein identifying the selected one of the first and second image signals to output to the image processing circuitry comprises:

determining whether the first image signal exceeds a predetermined threshold; and

in response to determining that the first image signal exceeds the predetermined threshold, overwriting the first image signal on the memory circuit with the second image signal; and

with the readout circuitry, outputting the identified image signal to the image processing circuitry.

10. The method defined in claim 9 , wherein identifying the selected one of the first and second image signals to output to the image processing circuitry further comprises:

in response to determining that the first image signal exceeds the predetermined threshold, labeling the first image signal with an indication bit that instructs the readout circuitry to overwrite the first image signal on the memory circuit with the second image signal.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2015
From: NAKAMURA, JUNICHI; MATSUO, SHINICHIRO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 035249/0018 →
Continuity (2)
Provisional Application 61870334 · Aug 27, 2013
Related Publication 20150062364A1 · Mar 5, 2015