Memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.
1. A memory device, comprising:
a first electrode;
a second electrode coupled to the first electrode through a resistance switching material, selectable between a first state, and a second state with higher resistance than the first state, wherein the resistance switching material forms a ring-like structure having a plurality of portions, and wherein each of the portions comprises a respective one of a plurality of cells of the memory device.
2. The memory device of claim 1 , further comprising:
a rectifying device coupled to the first electrode.
3. The memory device of claim 2 , further comprising:
an access transistor coupled to a side of the resistance switching material opposite from the rectifying device.
4. A memory device, comprising:
an electrode coupled to another electrode through a resistance switching material, selectable between a first state, and a second state with higher resistance than the first state, wherein the resistance switching material forms a ring-like structure having a plurality of portions, and wherein each of the portions comprises a respective one of a plurality of cells of the memory device; and
a rectifying device coupled to the other electrode.
5. The memory device of claim 4 , wherein the plurality of cells comprises two cells.
6. The memory device of claim 4 , wherein the plurality of cells comprises four cells.
7. The memory device of claim 4 , wherein the rectifying device comprises a diode.
8. The memory device of claim 4 , wherein the rectifying device comprises one of a plurality of rectifying devices.
9. The memory device of claim 4 , wherein the rectifying device is located between an electrode select line and the other electrode.
10. The memory device of claim 4 , wherein the rectifying device is located between the other electrode and the resistance switching material.
11. The memory device of claim 4 , wherein the resistance switching material comprises a phase change material capable of changing between a first conductive phase and a second conductive phase that is less conductive than the first conductive phase.
12. The memory device of claim 11 , wherein the phase change material comprises a chalcogenide glass.
13. A memory device, comprising:
a plurality of first electrodes; and
a plurality of multicell blocks, each including a plurality of second electrodes coupled to a respective one of the plurality of first electrodes by a resistance switching material capable of changing between a first conductive state and a second state that is less conductive than the first state, wherein the resistance switching material forms a ring-like structure having a plurality of portions, and wherein each of the portions comprises a respective one of a plurality of cells of the memory device.
14. The memory device of claim 13 , further comprising:
a plurality of rectifying structures respectively coupled to the plurality of multicell blocks.
15. The memory device of claim 14 , wherein the plurality of rectifying structures are located between a plurality of electrode select lines and the first electrodes.
16. The memory device of claim 14 , wherein the plurality of rectifying structures are located between the plurality of first electrodes and a phase change material.
17. The memory device of claim 14 , wherein the plurality of rectifying structures comprise a plurality of diodes.
18. The memory device of claim 14 , wherein the plurality of rectifying structures comprise a plurality of rectifying devices for each multicell block.