Semiconductor device with buried bit line and method for fabricating the same

1. A method for fabricating a semiconductor device, the method comprising:

etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate;

forming a supporter in each of the bulb-type trenches;

dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and

forming a bit line in each body line of the pair of body lines,

wherein the dividing of each active region into a pair of body lines comprises:

partially etching a thickness of each active region to form the trenches;

forming spacers on sidewalls of the trenches;

etching surfaces of the plurality of active regions that define bottom surfaces of the trenches to increase a depth of the trenches; and

etching sidewalls, which define the trenches, of the pair of body lines to form recessed lower sidewalls extending in a direction perpendicular to a longitudinal direction of the trenches.

2. The method of claim 1 , further comprising:

forming a conductive layer in the trenches so that the recessed lower sidewalls are buried by the conductive layer; and

removing the conductive layer from the trenches, except for the recessed lower sidewalls to form buried bit lines in the recessed lower sidewalls of the body lines.

3. A method for fabricating a semiconductor device, the method comprising:

forming an insulation layer on a semiconductor substrate;

forming a conductive layer on the insulation layer;

etching the conductive layer to form first trenches that define a plurality of active regions;

forming a supporter in each of the trenches;

dividing each active region, of the plurality of active regions, into a pair of body lines by forming a second trench through each active region; and

forming a bit line in each body line of the pair of body lines.

4. The method of claim 3 , further comprising:

after forming the bit lines, etching the pair of the body lines to form a pair of pillars, where the pair of pillars each include channel region; and

forming a capacitor connected to an upper portion of each pillar.

5. The method of claim 3 , wherein the supporters comprise an insulation material.

6. The method of claim 3 , wherein the dividing of each active region into a pair of body lines comprises:

partially etching a thickness of each active region to form the second trenches;

forming spacers on sidewalls of the second trenches; and

etching surfaces of the plurality of active regions that define bottom surfaces of the second trenches to form recessed lower sidewalls extending in a direction perpendicular to a longitudinal direction of the second trenches.

7. The method of claim 6 , further comprising:

forming a metal layer in the trenches so that the recessed lower sidewalls are buried by the metal layer; and

removing the metal layer from the trenches, except for the recessed lower sidewalls, to form buried bit lines in the recessed lower sidewalls of the body lines.