Methods of fabricating semiconductor devices including interlayer wiring structures
Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask.
1. A method for fabricating a semiconductor device, comprising:
providing a first interlayer insulating layer;
forming a conductive contact plug that penetrates the first interlayer insulating layer;
forming a second interlayer insulating layer on the first interlayer insulating layer and the conductive contact plug;
forming a first interlayer wiring that penetrates the second interlayer insulating layer and that overlaps the conductive contact plug;
etching the second interlayer insulating layer using the first interlayer wiring as an etch mask until the conductive contact plug is exposed; and
etching an exposed portion of the conductive contact plug using the first interlayer wiring as the etch mask.
2. The method of claim 1 , farther comprising forming a third interlayer insulating layer on the first interlayer wiring.
3. The method of claim 2 , wherein forming the third interlayer insulating layer comprises forming an air gap in the third interlayer insulating layer.
4. The method of claim 1 , further comprising forming an etch stop layer on the first interlayer insulating layer and the conductive contact plug before forming the second interlayer insulating layer.
5. The method of claim 1 , wherein the first interlayer wiring comprises copper.
6. The method of claim 1 , further comprising forming a second interlayer wiring that penetrates the second interlayer insulating layer and that does not overlap the conductive contact plug,
wherein the exposed portion of the conductive contact plug is adjacent the second interlayer wiring so that etching the exposed portion of the conductive contact plug recesses the conductive contact plug away from the second interlayer wiring.
7. The method of claim 1 , wherein forming the first interlayer wiring comprises forming the first interlayer wiring so that the first interlayer wiring is formed on a side surface of the conductive contact plug.
8. The method of claim 7 , wherein etching the exposed portion of the conductive contact plug comprises etching opposing sides of the conductive contact plug.
9. The method of claim 1 , wherein the etching the exposed portion of the conductive contact plug comprises etching the conductive contact plug using wet etching.
10. The method of claim 9 , wherein the wet etching is performed using chlorine (Cl).
11. The method of claim 1 , wherein the conductive contact plug comprises a first material and the first interlayer wiring comprises a second material that has an etch selectivity relative to the first material.
12. The method of claim 11 , wherein the first material comprises polysilicon, a metal silicide compound, and/or a conductive metal nitride, and wherein the second material comprises copper.
13. The method of claim 1 , wherein etching the exposed portion of the conductive contact plug comprises isotropically etching the conductive contact plug.
14. A method of fabricating a semiconductor device, comprising:
providing a substrate in which a cell array region and a peripheral region are defined;
forming a memory device in the cell array region; and
forming an interlayer wiring in the peripheral region,
wherein forming the interlayer wiring comprises:
forming a copper wiring on a conductive contact plug, wherein the copper wiring overlaps the conductive contact plug; and
etching a portion of the conductive contact plug using the copper wiring as a mask.
15. The method of claim 14 , further comprising:
forming a landing pad that is electrically connected to a capacitor in the cell array region; and
forming a bit line that is electrically connected to the conductive contact plug, in the peripheral region,
wherein the landing pad and the bit line are formed simultaneously.
16. The method of claim 14 , further comprising forming a capacitor contact that is electrically connected to a capacitor in the cell array region,
wherein the conductive contact plug and the capacitor contact are formed simultaneously.
17. The method of claim 14 , wherein etching the exposed portion of the conductive contact plug comprises etching the exposed portion of the conductive contact plug using wet etching.
18. The method of claim 17 , wherein the wet etching is performed using chlorine (Cl).
19. A method of forming an interlayer wiring structure in a semiconductor device, the method comprising:
forming a conductive contact plug:
forming an interlayer wiring on the conductive contact plug, wherein the interlayer wiring overlaps the conductive contact plug;
etching an exposed portion of the conductive contact plug using the interlayer wiring as an etch mask.
20. The method of claim 19 , farther comprising forming a second interlayer wiring that does not overlap the conductive contact plug, wherein the exposed portion of the conductive contact plug is adjacent the second interlayer wiring so that etching the exposed portion of the conductive contact plug recesses the conductive contact plug away from the second interlayer wiring.